Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.

Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.

Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.

Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.

Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.

Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.

Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.

Abstract: A universally configurable pocket holster includes a pocket clip having a U-shaped bend with integrally formed front and rear legs in overlying relationship from the U-shaped bend with one leg having a small aperture, a first horizontal traversing strap with first and second surfaces with one surface being substantially covered with one fastener component of a hook and loop material and the other surface is substantially covered with the other fastener component of a hook and loop material, a second perpendicular traversing strap with first and second surfaces being substantially covered with one fastener component of a hook and loop material and the other surface is substantially covered with the other fastener component of a hook and loop material, and a fastening point that forms an axis connecting the traversing straps, and the pocket clip allowing for the assembly to slightly rotate or swing from one side to the other.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: A method of packaging a surgical implant is provided. The method includes receiving a portion of the surgical implant or a component coupled to the surgical implant at least partially within a recess of an implant holder. The recess includes a plurality of lobe shapes adapted to engage the implant or component. The recess only receives a top portion of the surgical implant or component couple to the surgical implant. The holder is inserted into a container. The holder has a first configuration in which the mouth of the recess is arranged to partially surround a portion of an implant or a component coupled to an implant. When the holder is at least partially received in the container, the recess grips the implant in a position spaced apart from the container. The holder also has a second configuration in which the mouth of the recess opens to release the implant.

Abstract: Converting a stale cache memory unique request to a read unique snoop response in a multiple (multi-) central processing unit (CPU) processor is disclosed. The multi-CPU processor includes a plurality of CPUs that each have access to either private or shared cache memories in a cache memory system. Multiple CPUs issuing unique requests to write data to a same coherence granule in a cache memory causes one unique request for a requested CPU to be serviced or “win” to allow that CPU to obtain the coherence granule in a unique state, while the other unsuccessful unique requests become stale. To avoid retried unique requests being reordered behind other pending, younger requests which would lead to lack of forward progress due to starvation or livelock, the snooped stale unique requests are converted to read unique snoop responses so that their request order can be maintained in the cache memory system.

Abstract: A wireless device configured as a group owner determines whether all client devices paired with the group owner are currently associated with the group owner. If all paired client devices are currently associated with the group owner, the group owner enters a first mode in which the group owner is in an active mode (powered up to communicate) during a first portion of a beacon interval and is in a low power mode (in which no communication occurs) during a second portion of the beacon interval. If not all paired client devices are currently associated with the group owner, the group owner enters a second mode in which the group owner is in the active state during the first portion and at least part of the second portion of the beacon interval. The group owner and client devices are configured to operate as master and slave.

Abstract: A technique for mapping logical threads to physical threads of a simultaneous multithreading (SMT) data processing system includes mapping one or more logical threads to one or more physical threads based on a selected SMT mode for a processor. In this case, respective resources for each of the one or more physical threads are predefined based on the SMT mode and an identifier of the one or more physical threads. The one or more physical threads are then executed on the processor utilizing the respective resources.

Abstract: Overhead associated with packet communication is reduced by combining or eliminating one or more fields of a packet. In some implementations, a reduction in overhead associated with packets employing security (e.g., IEEE 802.11ah packets) can be achieved by reducing overhead associated with verification-related fields. For example, a packet can include a merged frame check sequence (FCS) and an integrity check value (ICV). In some implementations, an FCS is omitted from a packet.

Abstract: A method of packaging a surgical implant is provided. The method includes receiving a portion of the surgical implant or a component coupled to the surgical implant at least partially within a recess of an implant holder. The recess includes a plurality of lobe shapes adapted to engage the implant or component. The recess only receives a top portion of the surgical implant or component couple to the surgical implant. The holder is inserted into a container. The holder has a first configuration in which the mouth of the recess is arranged to partially surround a portion of an implant or a component coupled to an implant. When the holder is at least partially received in the container, the recess grips the implant in a position spaced apart from the container. The holder also has a second configuration in which the mouth of the recess opens to release the implant.

Abstract: A package and method of packaging a surgical implant or surgical instrument are described. The package comprises a container and a holder having a recess arranged to receive a portion of a surgical implant or instrument, or a component coupled to the surgical implant or instrument. The holder is arranged to be at least partially received within the container. The holder has a first configuration in which the mouth of the recess is arranged to partially surround a portion of an implant or instrument, or a component coupled to the surgical implant or instrument, such that the recess grips the implant or instrument in position spaced apart from the container when the holder is at least partially received in the container. The holder also has a second configuration in which the mouth of the recess opens to release the implant or instrument.

Abstract: Operations for a WLAN-capable remote control device and a controlled device are disclosed. A first network device (e.g., remote control) may receive a user input for controlling operation of a second network device (e.g., controlled device) of a communication network. The first network device may transition to an active operating state in response to receiving the user input. The first network device may transmit the first user input to the second network device. The first network device may exit the active operating state in response to successfully transmitting the first user input to the second network device.

Abstract: An apparatus includes an electric motor including a rotor and a stator, and a compression device including a compression chamber and a compression mechanism. The compression chamber is within either the rotor or the stator of the electric motor.