Abstract: Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present invention relates to a control system for a power supply. The system includes a bias generator that provides a bias signal operative to charge a storage device based on a control signal. During a low power mode, a control system provides the control signal with a predetermined duty cycle that is functionally related to a storage capacity of the storage device.

Abstract: Systems and methods are disclosed to mitigate transient electrical energy that is supplied to a load. A power supply system can include a regulator that supplies regulated electrical energy to an associated load based on an operating mode of the system. A supplemental power supply supplies supplemental electrical energy to the associated load that varies over time to mitigate transient electrical characteristics in the electrical energy being supplied to the associated load due to an operating mode transition of the power supply system.

Abstract: Systems and methods are disclosed to mitigate a transient condition in electrical energy that is supplied to a load. A power supply system includes a converter that supplies regulated electrical energy to an associated load. A feedback network provides a reference signal based on the regulated electrical energy being supplied to the load, the regulator controlling the regulated electrical energy based on the reference signal. The feedback network is modified to adjust the reference signal so as to mitigate a transient condition in the regulated electrical energy.

Abstract: A solid state light apparatus ideally suited for use in traffic control signals provided with optical feedback to achieve a constant light output, preferably by detecting back-scattered light from a diffuser centered above an LED array. The control logic allows for the LEDs to be individually driven, and having their drive characteristics changed over time to ensure a uniform beam of light is generated at an intensity meeting DOT standards, across the life of the device. The optical feedback also establishes the uniform beam intensity level as a function of sensed ambient light to discern day and night operation.

Abstract: An apparatus, system and method for determining when an LED used in traffic signal device will fail. The traffic signal apparatus comprises a housing, a solid state light disposed therein and having an array of LED generating a light output therefrom, and a circuit adapted to predict failure of the solid state light source based on a plurality of parameters at which the LED array operates. The method comprises the acts of sensing the light output generated by the LED array and sensing the ambient temperature thereby. These sensing acts are then followed by a calculating act wherein a time-average temperature value is calculated based on the intensity of both the light output and the ambient temperature. The calculating act is then followed by another calculating act wherein a time-average duty cycle value of the power source powering the LED array is determined.

Abstract: A reconfigurable LED array (22) having LED sets (26, 28, 30) in series with a main LED array (24). The LED array (22) is controlled as a function of the operating DC voltage such that as the operating DC voltage level drops, selective ones of the LED strings are shunted so that the remaining LEDs of the array (22) are operational. The operational LEDs are PWM controlled such that the overall light intensity generated by the operational LEDs meets DOT requirements. The LED sets (26, 28 30) are connected in series with the main LED (24) as is stacked logic (62, 64) along with a voltage regulator (60).

Abstract: A stacked logic circuit (20) having a serially connected first logic circuit (12) operating off a first voltage differential and providing in series with a second logic circuit (14) operating off a second voltage differential. The second logic circuit being in series with the first logic circuit recycles the current of the first logic circuit. A low impedance shunt circuit (30) is provided in parallel with the first logic circuit (12) and shunts additional current required of and to the second logic circuit (14) from the single voltage source (VCC). A Zener diode (Z1) shunts current from the first logic circuit not required by the second logic circuit via a shunt node (N). The shunt circuit (30) includes a Darlington pair of transistors or a three terminal voltage regulator (42) and only shunts a very small amount of current to ground. The stacked logic circuit of the present invention efficiently uses current drawn by the single voltage source to reduce power consumption.

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.

Abstract: An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.

Abstract: A temperature compensation circuit (FIG. 5a) has a controlled temperature compensated voltage drop across R1. A Schottky diode D1 is connected to the base of Q1 through resistor R1. The temperature coefficients of the base-emitter junction of Q1 and the diode D1 have a predetermined differential, preferably none. The forward voltage drop across D1 and the base-emitter junction are different, thereby establishing a controlled current through resistor R1 that is independent of temperature.