Patents by Inventor Kevin P. Lyne

Kevin P. Lyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110193200
    Abstract: A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling.
    Type: Application
    Filed: September 14, 2010
    Publication date: August 11, 2011
    Inventors: Kevin P. Lyne, Stanley Craig Beddingfield, Elida I. De Obaldia, Raymundo Monasterio Camenforte, David Charles Stepniak
  • Patent number: 7449364
    Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: November 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Kevin P. Lyne
  • Publication number: 20080258285
    Abstract: An insulating sheet-like substrate (601), which has on one surface (601a) a first patterned metal layer (605) with a first (603a) and a second (603b) array of contact pads. The pads of the first array have a first pitch center-to-center, and each pad has a first perimeter. The pads of the second array have a second pitch center-to-center, and each pad has the first perimeter. The substrate has on its other surface (601b) a second patterned metal layer (606) with a third array (607) of contact pads, which has the first pitch center-to-center, and each pad has a third perimeter. Conductive vias (640) between the first and the second metal layers connect contact pads and have a fourth perimeter; the vias are placed in interstitial locations so that the fourth perimeter does not intersect with the first and third perimeters. Vias in interstitial locations can be provided by disposing the first array and the third array so that the first and third perimeters of respective contact pads are concentrically aligned.
    Type: Application
    Filed: August 16, 2007
    Publication date: October 23, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peter R. Harper, James L. Turner, Kevin P. Lyne, Kurt Wachtler
  • Publication number: 20080153265
    Abstract: In one aspect, the method comprises etching a trench into a scribe street located between dies formed on a semiconductor wafer. The dies each have circuitry, and the etching is conducted to a depth within the semiconductor wafer that extends beyond a depth of the circuitry. The etch forms an edge of the die. A passivation layer is placed on the edge of the die. A back surface of the semiconductor wafer is removed until it intersects the trench, which separates the dies from the wafer. The removing process does not remove the passivation layer from the edge of the die.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Kevin P. Lyne
  • Patent number: 7105923
    Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: September 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Kevin P. Lyne
  • Publication number: 20030122254
    Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.
    Type: Application
    Filed: March 21, 2002
    Publication date: July 3, 2003
    Inventor: Kevin P. Lyne