Patents by Inventor Kevin P. McAuliffe

Kevin P. McAuliffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030004898
    Abstract: A method of negotiating an electronic commerce (e-commerce) transaction for the sale of a selected good can include identifying an asking price for the selected good and retrieving from memory merchant business objectives (MBOs) and consumer privacy rules (CPRs). The MBOs can specify incentive information corresponding to a proposed exchange of consumer information and the CPRs can specify asking prices corresponding to the proposed exchange of consumer information. The MBOs can be compared to the CPRs to determine if an agreement can be reached for the sale of the selected good with an incentive based upon the proposed exchange of consumer information. The e-commerce transaction for the sale of the selected good with the incentive can be consummated if in the comparing step it is determined that an agreement can be reached.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Kevin P. McAuliffe, Robert M. Szabo, James J. Toohey
  • Patent number: 5347652
    Abstract: Method and apparatus for use in a digital data processing system that evaluates functional networks. A method operates to assign a unique signature to each input constant of the network, assign a unique signature to each output of a network Function, and to store each of the constants and function outputs along with their assigned signatures. The signatures operate as an access key to the associated stored constants and function outputs, thereby eliminating a requirement to reevaluate a Function if its outputs already exist. A storage element, or Dictionary (20), stores data units, such as input data, intermediate values, and/or pointers to same, each with a unique signature. The storage element, in concert with a Dictionary Controller (18), provides for the deletion of a stored data unit that is associated with a specified signature and the retrieval of a stored data unit that is associated with a specified signature.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: September 13, 1994
    Assignee: International Business Machines Corporation
    Inventors: David A. Epstein, Glenn G. Gilley, Kevin P. McAuliffe
  • Patent number: 5313609
    Abstract: A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global directory associated with the main memory to keep track of state and control information of cache lines. Upon a request by a requesting cache for a cache line which has been exclusively modified by a source cache, two buffers are situated in the global directory to collectively intercept modified data words of the modified cache line during the write-back to memory. A modified word buffer is used to capture modified words within the modified cache line. Moreover, a line buffer stores an old cache line transferred from the memory, during the write back operation. Finally, the line buffer and the modified word buffer, together, provide the entire modified line to a requesting cache.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: May 17, 1994
    Assignee: International Business Machines Corporation
    Inventors: Sandra J. Baylor, Kevin P. McAuliffe, Bharat D. Rathi
  • Patent number: 5291442
    Abstract: A system is provided for management of data in cache memories in a multiprocessor environment which allows portions of lines to be valid and exclusive, while other portions are valid, but not exclusive, or invalid. A processor may store into portions of a line under its exclusive control without invalidating copies of the line held in the cache memories of the other processors. The system includes at least two processors, a shared main memory and a system control element, and each processor has a corresponding cache memory, a modified line stack and a sectored line directory. The modified line stack identifies data lines which have been changed since being made resident in cache memory. It also identifies the status of change of each word within those lines. A "shared exclusive" flag in the system control element identifies each line for which portions of the line are under exclusive control of more than one processor.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: March 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Joshua W. Knight, Kevin P. McAuliffe, James H. Pomerene, Rudolph N. Rechtschaffen, Frank J. Sparacio
  • Patent number: 4980822
    Abstract: A multiprocessing system is presented having a plurality of processing nodes interconnected together by a communication network, each processing node including a processor, responsive to user software running on the system, and an associated memory module, and capable under user control of dynamically partitioning each memory module into a global storage efficiently accessible by a number of processors connected to the network, and local storage efficiently accessible by its associated processor.
    Type: Grant
    Filed: March 16, 1988
    Date of Patent: December 25, 1990
    Assignee: International Business Machines Corporation
    Inventors: William C. Brantley, Jr., Kevin P. McAuliffe, Vern A. Norton, Gregory F. Pfister, Joseph Weiss
  • Patent number: 4969088
    Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements.
    Type: Grant
    Filed: April 26, 1988
    Date of Patent: November 6, 1990
    Assignee: International Business Machines Corporation
    Inventors: Kevin P. McAuliffe, Vern A. Norton, Gregory F. Pfister, Bharat D. Rathi
  • Patent number: 4885680
    Abstract: A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data.
    Type: Grant
    Filed: July 25, 1986
    Date of Patent: December 5, 1989
    Assignee: International Business Machines Corporation
    Inventors: John H. Anthony, William C. Brantley, Jr., Kevin P. McAuliffe, Vern A. Norton, Gregory F. Pfister
  • Patent number: 4754394
    Abstract: A multiprocessing system is presented for dynamically partitioning a storage module into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including the interleaving of storage references output by a processor, under the control of that processor, and dynamically directing the storage references to first or second portions of the storage module.
    Type: Grant
    Filed: October 24, 1984
    Date of Patent: June 28, 1988
    Assignee: International Business Machines Corporation
    Inventors: William C. Brantley, Jr., Kevin P. McAuliffe, Vern A. Norton, Gregory F. Pfister, Joseph Weiss