Patents by Inventor Kevin P. O'Brien
Kevin P. O'Brien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112122Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: INTEL CORPORATIONInventors: Kevin P. O'Brien, Paul Gutwin, David L. Kencke, Mahmut Sami Kavrik, Daniel Chanemougame, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Uygar E. Avci, Tristan A. Tronic, Chelsey Dorow, Andrey Vyatskikh, Rachel A. Steinhardt, Chia-Ching Lin, Chi-Yin Cheng, Yu-Jin Chen, Tyrone Wilson
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Publication number: 20250113521Abstract: A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by a diffusion bonding layer. The direct transfer of TMD monolayers can be repeated to create a stack of TMD monolayers. A stack of TMD monolayers can be used in a field effect transistor, such as a nanoribbon field effect transistor.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Andrey Vyatskikh, Paul B. Fischer, Paul Killian Nordeen, Uygar E. Avci, Mahmut Sami Kavrik, Ande Kitamura, Kirby Maxey, Carl Hugo Naylor, Kevin P. O'Brien
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Publication number: 20250113573Abstract: A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. Transfer of the TMD monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the TMD monolayer from the growth substrate. The low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the TMD monolayer during lift-off. The carrier wafer and protective layer are separated from the TMD monolayer after attachment of the TMD monolayer to the target substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Andrey Vyatskikh, Paul B. Fischer, Uygar E. Avci, Chelsey Dorow, Mahmut Sami Kavrik, Karthik Krishnaswamy, Chia-Ching Lin, Jennifer Lux, Kirby Maxey, Carl Hugo Naylor, Kevin P. O'Brien, Justin R. Weber
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Publication number: 20250113599Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Kevin P. O'Brien, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Pratyush P. Buragohain, Chelsey Dorow, Mahmut Sami Kavrik, Wouter Mortelmans, Marko Radosavljevic, Uygar E. Avci, Matthew V. Metz
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Publication number: 20250107147Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Mahmut Sami Kavrik, Uygar E. Avci, Pratyush P. Buragohain, Chelsey Dorow, Jack T. Kavalieros, Chia-Ching Lin, Matthew V. Metz, Wouter Mortelmans, Carl Hugo Naylor, Kevin P. O'Brien, Ashish Verma Penumatcha, Carly Rogan, Rachel A. Steinhardt, Tristan A. Tronic, Andrey Vyatskikh
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Publication number: 20250006840Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Applicant: INTEL CORPORATIONInventors: Rachel A. Steinhardt, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Tristan A. Tronic, Ian Alexander Young, Matthew V. Metz, Marko Radosavljevic, Carly Rogan, Brandon Holybee, Raseong Kim, Punyashloka Debashis, Dominique A. Adams, I-Cheng Tung, Arnab Sen Gupta, Gauri Auluck, Scott B. Clendenning, Pratyush P. Buragohain, Hai Li
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Publication number: 20250006839Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drainType: ApplicationFiled: June 28, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Kevin P. O'Brien, Dmitri Evgenievich Nikonov, Rachel A. Steinhardt, Pratyush P. Buragohain, John J. Plombon, Hai Li, Gauri Auluck, I-Cheng Tung, Tristan A. Tronic, Dominique A. Adams, Punyashloka Debashis, Raseong Kim, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Marko Radosavljevic, Uygar E. Avci, Ian Alexander Young, Matthew V. Metz
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Publication number: 20250006841Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Arnab Sen Gupta, Dmitri Evgenievich Nikonov, John J. Plombon, Rachel A. Steinhardt, Punyashloka Debashis, Kevin P. O'Brien, Matthew V. Metz, Scott B. Clendenning, Brandon Holybee, Marko Radosavljevic, Ian Alexander Young, I-Cheng Tung, Sudarat Lee, Raseong Kim, Pratyush P. Buragohain
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Publication number: 20250006791Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.Type: ApplicationFiled: July 1, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Kevin P. O'Brien, Dominique A. Adams, Gauri Auluck, Pratyush P. Buragohain, Scott B. Clendenning, Punyashloka Debashis, Arnab Sen Gupta, Brandon Holybee, Raseong Kim, Matthew V. Metz, John J. Plombon, Marko Radosavljevic, Carly Rogan, Tristan A. Tronic, I-Cheng Tung, Ian Alexander Young, Dmitri Evgenievich Nikonov
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Publication number: 20250008852Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.Type: ApplicationFiled: July 1, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Punyashloka Debashis, Dominique A. Adams, Gauri Auluck, Scott B. Clendenning, Arnab Sen Gupta, Brandon Holybee, Raseong Kim, Matthew V. Metz, Kevin P. O'Brien, John J. Plombon, Marko Radosavljevic, Carly Rogan, Hojoon Ryu, Rachel A. Steinhardt, Tristan A. Tronic, I-Cheng Tung, Ian Alexander Young, Dmitri Evgenievich Nikonov
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Publication number: 20240429301Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.Type: ApplicationFiled: June 26, 2023Publication date: December 26, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Dmitri Evgenievich Nikonov, Kevin P. O'Brien, John J. Plombon, Tristan A. Tronic, Ian Alexander Young, Matthew V. Metz, Marko Radosavljevic, Carly Rogan, Brandon Holybee, Raseong Kim, Punyashloka Debashis, Dominique A. Adams, I-Cheng Tung, Arnab Sen Gupta, Gauri Auluck, Scott B. Clendenning, Pratyush P. Buragohain
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Publication number: 20240355768Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
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Publication number: 20240355934Abstract: Described herein are transistors with monolayer transition metal dichalcogenides (TMD) semiconductor material. TMD materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. A transistor has a single layer of TMD forming a channel region, and multiple layers of the TMD material at the source and drain regions. Upper portions of the multilayer TMD source and drain regions are doped, and conductive contacts are formed over the doped portions.Type: ApplicationFiled: April 21, 2023Publication date: October 24, 2024Applicant: Intel CorporationInventors: Mahmut Sami Kavrik, Tristan A. Tronic, Jennifer Lux, Uygar E. Avci, Kevin P. O'Brien
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Patent number: 12107060Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: GrantFiled: September 18, 2020Date of Patent: October 1, 2024Assignee: Intel CorproationInventors: Adel A. Elsherbini, Zhiguo Qian, Gerald S. Pasdast, Mohammad Enamul Kabir, Han Wui Then, Kimin Jun, Kevin P. O'Brien, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov, Feras Eid
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Patent number: 12062631Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: GrantFiled: September 18, 2020Date of Patent: August 13, 2024Assignee: Intel CorporationInventors: Adel A Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
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Publication number: 20240222482Abstract: Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. The doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Kevin P. O'Brien, Rachel Steinhardt, Chelsey Dorow, Carl H. Naylor, Kirby Maxey, Sudarat Lee, Ashish Verma Penumatcha, Uygar Avci, Scott Clendenning, Tristan Tronic, Mahmut Sami Kavrik, Ande Kitamura
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Publication number: 20240222506Abstract: An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Hojoon Ryu, Punyashloka Debashis, Rachel A. Steinhardt, Kevin P. O'Brien, John J. Plombon, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240222484Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Chia-Ching Lin, Kevin P. O'Brien, Ashish Verma Penumatcha, Chelsey Dorow, Kirby Maxey, Carl H. Naylor, Tao Chu, Guowei Xu, Uygar Avci, Feng Zhang, Ting-Hsiang Hung, Ande Kitamura, Mahmut Sami Kavrik
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Publication number: 20240186416Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.Type: ApplicationFiled: January 16, 2024Publication date: June 6, 2024Inventors: Kevin P. O'Brien, Carl NAYLOR, Chelsey DOROW, Kirby MAXEY, Tanay GOSAVI, Ashish Verma PENUMATCHA, Shriram SHIVARAMAN, Chia-Ching LIN, Sudarat LEE, Uygar E. AVCI
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young