Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run a ML model, receiving synchronization information for organizing the running of the ML model with other ML models, determining, based on the synchronization information, to delay running the ML model, delaying the running of the ML model, determining, based on the synchronization information, a time to run the ML model; and running the ML model at the time.

Abstract: A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an ADC (analog-to-digital converter). The samples can be aggregated as a distribution in order to estimate the jitter of the input clock signal. Variability of the measurement system can be minimized through calibrating the device-under-test at specific points of PVT (process, voltage, and temperature) conditions. A confidence metric such as a standard of deviation can be derived from the associated samples. The measurement system can be included on a substrate that includes the oscillator that generates the input clock signal.

Abstract: A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period.

Abstract: Low-frequency digital data input signals in an integrated circuit are controlled between first and second stages in a signal input path of the integrated circuit by a capacitance in the signal input path between the first and second stages. The capacitance is sized to attenuate high-frequency noise in the signal input path. In one embodiment, the integrated circuit may be an input buffer circuit in which the capacitance is a capacitor between the signal input path and a reference potential, a voltage source, or both. In another embodiment, the integrated circuit may be an oscillator circuit in which the capacitance is provided between corresponding elements of a differential pair of transistors in the first stage.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period.

Abstract: A modulation evaluation system associated with frequency modulations periods of a phase-locked loop is described. The system includes a first accumulator for accumulating clock edges a window of the frequency modulation periods; a second accumulator coupled to the first accumulator and operative for accumulating clock edges during whole periods of the frequency modulation periods; a dynamic enable control coupled to a first input associated with the first accumulator and a second input associated with the second accumulator, wherein the dynamic enable control selectively transmits a first enable signal that controls when the first accumulator accumulates clock edges and a second enable signal controls when the second accumulator accumulates clock edges, and accumulating clock edges enable modulation evaluation during production.