Abstract: In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.

Abstract: In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.

Abstract: A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.

Abstract: In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.