Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.

Abstract: Methods, systems, and devices for peak power control of a memory system are described. The method may include operating the memory system according to a first policy for managing power consumed by the memory system. In some examples, the first policy may be based on a ratio between a peak power consumed by the memory system and an average power consumed by the memory system over a duration. Further, the method may include monitoring one or more power characteristics associated with operating the memory system and operating the memory system according to a second policy for managing the power consumed by the memory system based on the one or more power characteristics satisfying a condition. In some examples, operating the memory system according to the second policy may include activating a peak power management (PPM) feature of the memory system.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to receive information from a host about invalidated memory addresses. The controller receives, from a host, data identifying a set of storage locations associated with invalidated data stored in a set of memory components and, in response to receiving the data, performs staging activity for the invalidated data stored in the set of storage locations. The controller receives, from the host, a trim command for one or more storage locations in the set of storage locations and performs trim operations for the one or more storage locations for which the staging activity has already been performed.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to control storage on the memory sub-system based on endurance of memory components. The controller groups the set of memory components into a plurality of categories representing different endurance levels of the set of memory components and communicates, to a host, information about the plurality of categories. The controller receives, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and an individual category associated with the individual memory component.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to configure data storage policies on the memory sub-system. The controller receives, from a host, a data storage policy instruction, the data storage policy instruction defining how data is stored on a set of memory components. The controller updates configuration information for the memory sub-system based on the data storage policy instruction received from the host and controls storage of data to the set of memory components based on the updated configuration information.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to deallocate data prior to folding operations. The controller generates an instruction to fold data stored in an individual portion of the set of memory components. The controller, prior to executing the instruction to fold the data stored in the individual portion of the set of memory components, transmits a communication to a host indicative of the instruction to fold the data stored in the individual portion. The controller conditions execution of the instruction to fold the data stored in the individual portion of the set of memory components based on transmission of the communication to the host.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to inform a host about write amplification penalty for host invalidations. The controller generates a virtual memory group comprising a portion of a memory component of a set of memory components. The controller computes a write amplification penalty associated with invalidating data associated with the virtual memory group. The controller communicates, to a host, information about the write amplification penalty associated with invalidating data associated with the virtual memory group. The controller receives, from the host, a request to invalidate data associated with the virtual memory group, the request being generated by the host based on the write amplification penalty.

Abstract: A processing device in a memory sub-system identifies a read error associated with a block and initiates a diagnostic memory access operation on the block. The processing device determines whether the diagnostic memory access operation was successfully performed on the block. Responsive to determining the diagnostic memory access operation was successfully performed on the block, the processing device initiates a diagnostic read operation on the block. The processing device determines whether the diagnostic read operation was successfully performed on the block. Responsive to determining the diagnostic read operation was successfully performed on the block, the processing device identifies the block as a healthy block.

Abstract: A processing device in a memory sub-system determines a total power-off time of a memory sub-system and identifies a configurable power-off time threshold for the memory sub-system. The processing device determines whether the total power-off time satisfies a threshold criterion based on the configurable power-off time threshold, responsive to determining that the total power-off time satisfies the threshold criterion, causes the memory sub-system to enter a relaxed block retirement mode of operation.

Abstract: Data is read from a set of memory cells of a memory device to a buffer of the memory device. One or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. The decoder corrects the one or more bits in error by decoding the data stored by the buffer. The decoding of the data results in corrected data. An encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.

Abstract: Exemplary methods, apparatuses, and systems include a media temperature manager receiving operating temperature measurements for a memory subsystem. The media temperature manager generates an average temperature using the operating temperature measurements. The media temperature manager determines that the average temperature satisfies a first value for a dynamic temperature threshold. The dynamic temperature threshold indicates a temperature at which the memory subsystem throttles media operations. The media temperature manager increases the dynamic temperature threshold to a second value in response to the average temperature satisfying the first value for the dynamic temperature threshold.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.

Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.

Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.