Abstract: A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.

Abstract: A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.

Abstract: A memory having built-in self repair with column shifting is provided. The total single columns are divided into smaller column groups and a bad column group is repaired with a redundant column group. Each column group is multiplexed into a pair of column group bitlines, which are fed into a shift circuit for the column group and a shift circuit for an adjacent column group. The shift circuit for the column group nearest the redundant column group receives the bitlines for that column group and the redundant column group bitlines. If a bad column group is detected, then starting with the column group furthest from the redundant column group, the shift circuit for each column group before the bad column group is deactivated. The shift circuit for the bad column group and the shift circuit for each column group after the bad column group are activated. Therefore, the bad column group is shifted out of the memory and the redundant column group fills the void.

Abstract: A semiconductor memory layout definition for connection to a power supply bus in an integrated circuit layout pattern. The layout definition includes an outline and a plurality of power supply conductor segments within the outline. At least one of the power supply conductor segments has a direct strap identifier which indicates a desired attachment to the power supply bus. The direct strap identifier is passed to a routing design tool which routes a direct strap conductor from the power supply bus to the power supply conductor segments having the direct strap identifier.

Abstract: A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized.