Abstract: Aspects of the present disclosure include a scalable proportional to absolute temperature (PTAT) hybrid circuit, comprising a bias mirror circuit configured to provide a zero temperature coefficient (ZTC) current, a PTAT control circuit configured to generate, based on the ZTC current, a PTAT current with a slope having a non-zero value, alter the PTAT current by at least scaling the PTAT current or changing the slope of the PTAT current to generate an altered PTAT current, and provide the altered PTAT current, a hybrid circuit configured to receive the ZTC current and the altered PTAT current, and output a larger current of the ZTC current and the altered PTAT current as a hybrid current.

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

Abstract: The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.

Abstract: The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.

Abstract: The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag.