Patents by Inventor Kevin Robert Bowles

Kevin Robert Bowles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed level-shifting multiplexer
    Patent number: 9806717
    Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
  • HIGH-SPEED LEVEL-SHIFTING MULTIPLEXER
    Publication number: 20170026044
    Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
  • High-speed level-shifting multiplexer
    Patent number: 9490813
    Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 8, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
  • HIGH-SPEED LEVEL-SHIFTING MULTIPLEXER
    Publication number: 20160134286
    Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Inventors: Kevin Robert Bowles, Jose Gabriel Corona, Venugopal Boynapalli
  • Method and apparatus for dynamic power saving with flexible gating in a cross-bar architecture
    Patent number: 9189438
    Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hari Rao, Venugopal Boynapalli, Kevin Robert Bowles, Vijay Bantval
  • REDUCED-AREA ARCHITECTURE FOR ASYMMETRIC INTERCONNECT
    Publication number: 20150161067
    Abstract: A reduced-area interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce area and energy consumption. Tri-state buffers inserted into XBAR data paths are configured to direct data between clients and sources on a number of data paths corresponding to the lesser of the number of clients and the number of sources. Interface area and power consumption is reduced by eliminating paths that are not always being used.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Kevin Robert BOWLES, Hari Madhava RAO, Sei Seung YOON
  • METHOD AND APPARATUS FOR DYNAMIC POWER SAVING WITH FLEXIBLE GATING IN A CROSS-BAR ARCHITECTURE
    Publication number: 20140281112
    Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Hari Rao, Venugopal Boynapalli, Kevin Robert Bowles, Vijay Bantval