Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Abstract: According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Abstract: According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Abstract: A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Abstract: A plurality of programmable logic blocks are programmed in a first configuration to perform one or both of an access function and a management function with respect to a plurality of non-volatile memory modules. A high data transfer rate connection is provided to an external random access memory device, wherein said at least a subset of said programmable logic blocks are programmed in said first configuration to perform one or both of said access function and said management function at least in part using data sent via a communication interface, wherein the communication interface is coupled to at least a subset of said programmable logic blocks.

Abstract: A storage server uses a semantic processor to parse and respond to client requests. A direct execution parser in the semantic processor parses an input stream, comprising client storage server requests, according to a defined grammar. A semantic processor execution engine capable of manipulating data (e.g., data movement, mathematical, and logical operations) executes microcode segments in response to requests from the direct execution parser in order to perform the client-requested operations. The resulting operational efficiency allows an entire storage server to be collapsed in some embodiments into a few relatively small integrated circuits that can be placed on a media device's printed circuit board, with the semantic processor itself drawing perhaps a few Watts of power.

Abstract: A device has an input port to allow the device to receive data. The device also has a parser to parse the data in response to symbols in a parser stack, determine when a symbol is a debug non-terminal symbol, and notify the device via an interrupt. The interrupt causes the device to gather information about the state of the parser at the time of encountering the non-terminal symbol.

Abstract: A system and method for isolating TCP comprises a proxy configured to manage a plurality of sessions including at least one transmission control protocol session, wherein the proxy translates data between the transmission control protocol session and a local session.

Abstract: An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.

Abstract: A network processing device provides a novel architecture for conducting firewall and other network interface management operations. In another aspect of the invention, a Unified Policy Management (UPM) architecture uses a same memory and processing structure to integrate firewall policy management with routing and switching decisions. In another embodiment, a Reconfigurable Semantic Processor (RSP) uses a parser to identify different syntactic elements that are then used by one or more Semantic Processing Units (SPUs) to carry out different firewall, network interface, routing, switching, and other packet processing operations.

Abstract: A firewall device provides a novel architecture for conducting firewall and other network interface management operations over a wired Ethernet connection. The firewall device includes a first network interface for connecting to a first packet switched network connection that transports packets, a second network interface for connecting to a second packet switched network connection that transports packets, and firewall circuitry configured to perform firewall operations on the packets transported between the first and second network interfaces and being powered entirely through power received through one of the first and second network interfaces over one of the first or second packet switched network connections.

Abstract: A computer architecture uses a PushDown Automaton (PDA) and a Context Free Grammar (CFG) to process data. A PDA engine maintains semantic states that correspond to semantic elements in an input data set. The PDA engine does not have to maintain a new state for each new character in a target search string and typically only transitions to a new state when the entire semantic element is detected. The PDA engine can therefore use a smaller and more predictable state table than DFA algorithms. Transitions between the semantic states are managed using a stack that allows multiple semantic states to be represented by a single nested non-terminal symbol.

Abstract: A system and method comprising a buffer configured to receive a data stream, a parser configured to parse the data stream from the buffer, and one or more processing units configured to co-process the data stream from the buffer responsive to the parsing by the parser, and then provide at least a portion of the processed data stream back to the buffer for additional parsing by the parser.

Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Abstract: A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a table interface configured to retrieve one or more production rules from a production rule table according to the parsing symbols, and a state machine configured to control the parsing of a data stream according to the retrieved production rules.

Abstract: Embodiments of a multiple-parsing-context parser and semantic processor are shown and described. The described embodiments allow an input data stream to be parsed in multiple contexts, with the parser switching between contexts as the input data stream dictates. For instance, one embodiment allows a SONET input data stream, including multiple interleaved payloads and SONET transport overhead, to be parsed using multiple grammars, with control passing between the grammars and contexts in a single pass. This approach allows a reconfigurable semantic processor to serve different payload arrangements for a complex multiplexed SONET stream.

Abstract: A device comprises a plurality of interface circuits for communicating between a semantic processor and a memory. Each interface circuit is configured for receiving lookup requests from the semantic processor. The device further comprises a buffer for allocating an interface circuit, if available, to the semantic processor. The allocated interface circuit is selected to access the memory for processing the lookup request.

Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.

Abstract: A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.