Patents by Inventor Kevin Roy Nunn

Kevin Roy Nunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6984869
    Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Sean Christopher Erickson, Kevin Roy Nunn, Jonathan Alan Shaw
  • Patent number: 6909591
    Abstract: An improved semiconductor capacitor and a method for fabricating the capacitor. The capacitor is located on a substrate having a first conductive section with a first outer plate connected to a first inner plate. A second conductive section having a second outer plate connected to a second inner plate is present in the capacitor. The second inner plate is located within a first hole in the first outer plate and the first inner plate is located within a second hole in the second outer plate such that a first distance is present between the second inner plate and the first outer plate and a second distance is present between the first inner plate and the second outer plate. Multiple layers of sections like the first conductive section and the second conductive section are stacked over each other and are connected to each other as part of the capacitor. Via connections may be used to connect the layers.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: June 21, 2005
    Assignee: LSI Logic Corporation
    Inventors: Sean Christopher Erickson, Kevin Roy Nunn, Eric Ray Miller