Abstract: A multi-loop voltage regulator with load tracking compensation includes a first closed-loop feedback network configured to receive a supply voltage from a power supply and drive an output voltage that is smaller than the supply voltage to a load. The multi-loop voltage regulator includes a second closed-loop feedback network connected to the first closed-loop feedback network and configured to regulate the output voltage between a first supply voltage rail and a second supply voltage rail for a given load current, in which the second closed-loop feedback network produces a gain that is greater than that of the first closed-loop feedback network. The multi-loop voltage regulator also includes a load tracking compensation circuit configured to detect a load current, and to increase the gain of the second closed-loop feedback network based on a dominant pole in the second closed-loop feedback network being a function of the detected load current.

Abstract: A multi-loop voltage regulator with load tracking compensation includes a first closed-loop feedback network configured to receive a supply voltage from a power supply and drive an output voltage that is smaller than the supply voltage to a load. The multi-loop voltage regulator includes a second closed-loop feedback network connected to the first closed-loop feedback network and configured to regulate the output voltage between a first supply voltage rail and a second supply voltage rail for a given load current, in which the second closed-loop feedback network produces a gain that is greater than that of the first closed-loop feedback network. The multi-loop voltage regulator also includes a load tracking compensation circuit configured to detect a load current, and to increase the gain of the second closed-loop feedback network based on a dominant pole in the second closed-loop feedback network being a function of the detected load current.

Abstract: A method and apparatus for providing quadrature biasing for coupled-pair circuits. A QBCP-circuit for quadrature amplifiers provides a new input common-mode sense point that separates the inputs for the differential-and-common mode feedback-control loops. The QBCP circuit biases all four transistors equivalently and reduces the feedback-loop interaction, thereby simplifying the bias control system and improves the voltage-transfer frequency-response performance.

Abstract: Arm electronics (AE) suitable for use in a disk drive are disclosed. The AE has write circuitry configured to operate the AE in a write mode during which a write mode supply current is drawn, and read circuitry configured to operate the AE in a read mode during which a read mode supply current is drawn. The AE uses a decaying current pulse generator that generates a decaying current pulse at the beginning of each write-to-read mode transition. The decaying current pulse has an initial value that is equal to the difference between the write mode supply current and the read mode supply current. This controlled load forces the AE to draw a gradually decreasing supply current for each write-to-read mode transition such that supply voltage transients (otherwise present due to parasitics in cabling between the AE and power supply) are reduced. Thus, the undesirable effects of such transients in the read circuitry are reduced so that write-to-read mode recovery times can be shortened.

Abstract: A method and apparatus for providing matched differential MR biasing and pre-amplification. Tightly matched and well centered low-level MR bias voltage is provided directly to the sensing element for controlled input-impedance differential pre-amplification without common-mode voltage level control with loops.

Abstract: A method and apparatus for providing matched differential MR biasing and pre-amplification. Tightly matched and well centered low-level MR bias voltage is provided directly to the sensing element for controlled input-impedance differential pre-amplification without common-mode voltage level control with loops.

Abstract: A method and apparatus for providing quadrature biasing for coupled-pair circuits. A QBCP-circuit for quadrature amplifiers provides a new input common-mode sense point that separates the inputs for the differential-and-common mode feedback-control loops. The QBCP circuit biases all four transistors equivalently and reduces the feedback-loop interaction, thereby simplifying the bias control system and improves the voltage-transfer frequency-response performance.

Abstract: Arm electronics (AE) suitable for use in a disk drive are disclosed. The AE has write circuitry configured to operate the AE in a write mode during which a write mode supply current is drawn, and read circuitry configured to operate the AE in a read mode during which a read mode supply current is drawn. The AE uses a decaying current pulse generator that generates a decaying current pulse at the beginning of each write-to-read mode transition. The decaying current pulse has an initial value that is equal to the difference between the write mode supply current and the read mode supply current. This controlled load forces the AE to draw a gradually decreasing supply current for each write-to-read mode transition such that supply voltage transients (otherwise present due to parasitics in cabling between the AE and power supply) are reduced. Thus, the undesirable effects of such transients in the read circuitry are reduced so that write-to-read mode recovery times can be shortened.

Abstract: A method and apparatus for high voltage applications, with the latest MOSFET technology having limited terminal-to-terminal voltage capability, includes a switch circuit having at least two serially coupled MOSFETs and a two-stage MOSFET connection using a plurality of resistors, and/or a bipolar transistor, and a plurality of diodes. One of the high voltage applications is a high speed write driver in a computer disk drive. The switch circuit switches on/off between zero volt and a voltage higher than a maximum terminal-to-terminal voltage of a single MOSFET which is typically five volts. A required voltage in high voltage applications can be in excess of, for example, 8 or 9 volts.

Abstract: A method and apparatus for high voltage applications, with the latest MOSFET technology having limited terminal-to-terminal voltage capability, includes a switch circuit having at least two serially coupled MOSFETs and a two-stage MOSFET connection using a plurality of resistors, and/or a bipolar transistor, and a plurality of diodes. One of the high voltage applications is a high speed write driver in a computer disk drive. The switch circuit switches on/off between zero volt and a voltage higher than a maximum terminal-to-terminal voltage of a single MOSFET which is typically five volts. A required voltage in high voltage applications can be in excess of, for example, 8 or 9 volts.

Abstract: A method and system are disclosed for controlling the application of a reset voltage pulse to a GMR sensor in a direct-access storage device (DASD), such that existing data is not damaged or altered. Each sensor is positioned or parked at a location reserved for reset pulse application, where no valid data is stored. A complex interrelated set of commands is then initiated, and upon completion of the entire set of interrelated commands, a reset pulse is applied to the GMR sensor. Any variation or interruption in the complex interrelated set of commands will result in a disarming of the reset pulse circuitry, effectively preventing an accidental or inadvertent application of the GMR reset pulse. Alternately, a group of GMR sensors each may be tracked to a reserve track, forming a reserve cylinder. Servo marks on the reserve track are sensed by a selected sensor and utilized to ensure no valid data is present.

Abstract: The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately at ground; and translating the input signal to a second state in a second logic level, the second state being above ground. The method and system translates a signal from a chip with a negative substrate bias. In the preferred embodiment, the method and system of the present invention uses a translation circuit to translate and drive the signal off-chip. The translation circuit in accordance with the present invention functions with a positive Vcc and a Vee lower than ground, and also does not violate any of the rules of functionality for components used in a chip which has a negatively biased substrate and a voltage limit on its components.

Abstract: An apparatus and method for sensing and reporting connection integrity of a differential transmission line having proper parallel termination is constructed by generating an error signal which indicates that one or both differential input lines are open. The error signal is generated using a voltage comparator having a first and second input in which these inputs are coupled to the first and second ECL signal lines. The first and second input lines are also coupled to a supply voltage by a first and second dynamic impedance such that the input is pulled high when the signal lines are open. The comparator generates an error signal when the input voltages are greater than voltages normally seen on the signal lines indicating the presence of a open transmission line.

Abstract: The present invention concerns an apparatus, method, and article of manufacture that satisfies the need for verifying the identity of a designated head in a gang servo head environment by querying a control parameter unit. In one embodiment, the invention may be implemented to provide a method to increase head select robustness for group head systems controlled by drive electronics. The method is practiced when a request is made for a designated head to perform a read or write operation. The request is received by a control parameter unit included in an arm electronics unit. The control parameter unit is then queried to verify the identity of the arm electronics unit selected. The identity of the designated head is then received. A parity check of the control data is performed and, assuming no errors, an actuating arm containing the designated head is positioned. The selected arm electronics unit is loaded with read or write data copied from a host system and transferred to or from the storage device.