Abstract: Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. The new code associated with the initialized memory is generated. At least one of the new code and the coherence code is executed. Other embodiments may be described and claimed.

Abstract: Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. The new code associated with the initialized memory is generated. At least one of the new code and the coherence code is executed. Other embodiments may be described and claimed.

Abstract: Embodiments include a system for supporting the sharing of volatile data between processors, caches and similar devices to minimize thrashing of a data structure tracking shared data. The system may include a modified, exclusive and shared volatile state. The system may also include a volatile load or read command.

Abstract: A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a speculative thread would execute desirably. The fork predictor may be implemented as a modified branch predictor circuit, and may have execution history updates entered by a determination of whether or not the execution of a speculative thread was or would have been desirable.

Abstract: The present invention relates to a conveyor belt cleaning apparatus for use with belt conveyors. The invention provides a conveyor belt cleaning apparatus (1) for use with a belt conveyor, the cleaning apparatus comprising a first arm (20a) and a second arm (20b) adapted to support a scraping blade (30), the first and second arms being rotatably mounted on a shaft (2) for independent rotation about an axis, the rotation of the arms causing corresponding positional adjustments of the scraping blade (30) with respect to the belt. The mountings (21a, 21b) of each arm (20a, 20b) on the shaft (2) includes a biasing means which, in use, acts to bias the arms towards the conveyor belt. The apparatus further includes an intermediate arm (40) located midway between the first arm (20a) and the second arm (20b) one end of which is connected to the shaft (2) and the opposing end of which is connected to the scraping blade (30) to provide support for the scraping blade (30).

Abstract: A mechanism for increasing the performance of control speculation comprises executing a speculative load, returning a data value to a register targeted by the speculative load if it hits in a cache, and associating a deferral token with the speculative load if it misses in the cache. The mechanism may also issue a prefetch on a cache miss to speed execution of recovery code if the speculative load is subsequently determined to be on the control flow path.

Abstract: The invention provides a method comprising monitoring an indicator indicating a usage of data speculatively loaded by a processor as a result of executing a speculative instruction; and selectively executing said speculative instruction when it is next encountered as an instruction pointer based on said usage. According to another embodiment, the invention provides a processor comprising a monitoring mechanism to monitor an indicator indicating a usage of data speculative loaded by said processor as a result of executing a speculative instruction; and a speculation control mechanism to selectively execute said speculative instruction when it is next encountered at an instruction pointer based on said usage.