Abstract: A method, a statistics subsystem, and a system use a combination of commercially available high speed memory and high density low speed memory to mitigate cost, space, control, and power issues associated with storing counters for statistics updates, while meeting the growing width and depth needs of multi-hundred gigabit Carrier Class data network devices. The method, statistics subsystem, and system offer a Counter Management Algorithm (CMA) that relies on rollover bits stored within data of counters. An update to the low speed memory is substantially faster than a rollover time for the counter in the high speed memory thereby allowing statistics to be cached in the high speed memory while updates take place to the low speed memory.

Abstract: An apparatus and method for efficiently performing error control coding tasks. An important aspect of the present invention is the provision of an ECC engine that responds to a specialized ECC instruction set having a plurality of instructions, such as a convolutional encoding instruction, a convolutional decoding instruction, and a cyclic redundancy code (CRC) instruction. The ECC engine has a plurality of functional building blocks (e.g., a configurable convolutional encoding functional block, a convolutional configurable decoding functional block, and a configurable cyclic redundancy check (CRC) functional block) that can be programmed or configured. A single instruction provided to the error control coding engine configures one of the functional blocks to execute a error control coding algorithm specified by the instruction. Each instruction also includes a plurality of fields that can be modified by the user.