Abstract: A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

Abstract: A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

Abstract: A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

Abstract: Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

Abstract: A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

Abstract: A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

Abstract: The subject disclosure is directed towards layered substrate structures with aligned optical access to electrical devices formed thereon for laser processing and electrical device tuning. According to an embodiment, a layered substrate structure is provided that comprises an optical substrate having a first surface and a second surface and a patterned bonding layer formed on the second surface that comprises a bonding region and an open region, wherein the open region exposes a portion of the second surface. The layered substrate structure further comprises a device chip bonded to the patterned bonding layer via the bonding region and comprising at least one electrical component aligned with the optical substrate and the open region. The at least one electrical component can include for example, a thin film wire, an air bridge, a qubit, an electrode, a capacitor or a resonator.

Abstract: A method of removal of a first and second sacrificial layer wherein an O2 plasma or an O2-containing environment is introduced to a cavity and a gap region through a plurality of via holes in a cavity capping material.

Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.

Abstract: A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.

Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

Abstract: A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process.

Abstract: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.

Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.