Abstract: The present invention discloses a heterogeneous computation framework, of Association. Rule Mining (ARM) using Micron's Autotmata Processor (AP). This framework is based on the Apriori algorithm. Two Automaton designs are proposed to match and count the individual itemset. Several performance improvement strategies are proposed including minimizing the number of reporting vectors and reduce reconfiguration delays. The experiment results show up to 94× speed ups of the proposed AP-accelerated Apriori on six synthetic and real-world datasets, when compared with the Apriori single-core CPU implementation. The proposed AP-accelerated Apriori solution also outperforms the state-of-the-art multicore and GPU implementations of Equivalence Class Transformation (Eclat) algorithm on big datasets.

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract: A method of operating a finite state machine circuit can be provided by determining if a target sequence of characters included in a string of reference characters occurs within a specified difference distance using states indicated by the finite state machine circuit to indicate a number of character mis-matches between the target sequence of characters and a respective sequence of characters within the string of reference characters.

Abstract: A method of searching tree-structured data can be provided by identifying all labels associated with nodes in a plurality of trees including the tree-structured data, determining which of the labels is included in a percentage of the plurality of trees that exceeds a frequent threshold value to provide frequent labels, defining frequent candidate sub-trees for searching within the plurality of trees using combinations of only the frequent labels, and then searching for the frequent candidate sub-trees in the plurality of trees including the tree-structured data using a plurality of pruning kernels instantiated on a non-deterministic finite state machine to provide a less than exact count of the frequent candidate sub-trees in the plurality of trees.

Abstract: A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.

Abstract: The present invention introduces the development of a flexible CPU-AP (Computer Processing Unit-Automata Processor) computing infrastructure for mining hierarchical patterns based on Apriori algorithm. A novel automaton design strategy, called linear design, is described to generate automata for matching and counting hierarchical patterns and apply it on SPM (Sequential Pattern Mining). In addition, another novel automaton design strategy, called reduction design, is described for the disjunctive rule matching (DRM) and counting. The present invention shows performance improvement of AP SPM and DRM solutions and broader capability over multicore and GPU (Graphics Processing Unit) implementations of GSP SPM, and shows that AP SPM and DRM solutions outperform state-of-the-art SPM algorithms SPADE and PrefixSpan (especially for larger datasets).

Abstract: A hardware accelerated solution of the SPM (Sequential Pattern Mining) is proposed using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs) The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. The multi puss pruning strategy of the GSP is implemented is the APs fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90× and 29× speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit) GSP implementations, respectively.

Abstract: The present invention discloses a heterogeneous computation framework, of Association. Rule Mining (ARM) using Micron's Autotmata Processor (AP). This framework is based on the Apriori algorithm. Two Automaton designs are proposed to match and count the individual itemset. Several performance improvement strategies are proposed including minimizing the number of reporting vectors and reduce reconfiguration delays. The experiment results show up to 94× speed ups of the proposed AP-accelerated Apriori on six synthetic and real-world datasets, when compared with the Apriori single-core CPU implementation. The proposed AP-accelerated Apriori solution also outperforms the state-of-the-art multicore and GPU implementations of Equivalence Class Transformation (Eclat) algorithm on big datasets.

Abstract: A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract: A multi-threaded processor system, method, and computer program product capable of utilizing a register file cache are provided for simultaneously processing a plurality of threads. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a register file and a register file cache in communication with the register file.

Abstract: A system, method, and computer program product are provided for removing a register of a processor from an active state. In operation, an aspect of a portion of a processor capable of simultaneously processing a plurality of threads is identified. Additionally, a register of the processor is conditionally removed from an active state, based on the aspect.

Abstract: Dynamic warp subdivision (DWS), which allows a single warp to occupy more than one slot in the scheduler without requiring extra register file space, is described. Independent scheduling entities also allow divergent branch paths to interleave their execution, and allow threads that hit in the cache or otherwise have divergent memory-access latency to run ahead. The result is improved latency hiding and memory level parallelism (MLP).

Abstract: A system for allocating and de-allocating registers of a processor. The system includes a register file having plurality of physical registers and a first table coupled to the register file for mapping virtual register IDs to physical register IDs. A second table is coupled to the register file for determining whether a virtual register ID has a physical register mapped to it in a cycle. The first table and the second table enable physical registers of the register file to be allocated and de-allocated on a cycle-by-cycle basis to support execution of instructions by the processor.