Patents by Inventor Kevin Su

Kevin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110163927
    Abstract: An amplified antenna includes an antenna element configured to receive over-the-air television broadcast signals and an amplification circuit for amplifying those received signals. The amplified signal is transmitted via an RF output terminal through an RF cable to a second device that is compatible with smart antenna technology as prescribed by the EIC-909 standard, Antenna Control Interface. The amplified antenna further includes an EIC-909 type jack, into which one end of a modular connector cable conforming to the EIC-909 standard is connected. The opposite end of the modular connector cable is connected to the EIC-909 interface jack of the second device. The amplified antenna can then draw electrical power from the smart antenna control module of the second device through the modular connector cable to drive the amplification circuit.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 7, 2011
    Inventor: KEVIN SU
  • Patent number: 7087528
    Abstract: A method of forming shallow trench isolation includes etching trenches through a nitride layer, a polysilicon layer, and a pad oxide layer and into a semiconductor substrate. The trenches are filled with an oxide layer. A silicon oxynitride layer is deposited overlying the oxide layer and both these layers are polished away using a first slurry having high selectivity. A second polishing polishes away the oxide layer using a second slurry having a low selectivity. The nitride layer is removed and a third polishing is performed to planarize the oxide layer using a third slurry having high selectivity. Alternatively, the oxide layer is etched away except where it overlies the trenches. A first polishing is performed to polish away the oxide layer using a first slurry having a low selectivity. A second polishing is performed to polish away the oxide layer using a second slurry having high selectivity.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 8, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Juing-Yi Cheng, Kevin Su
  • Publication number: 20040048478
    Abstract: A method of forming shallow trench isolation using CMP is described. A pad oxide layer is grown overlying a silicon semiconductor substrate. A polysilicon layer is deposited overlying the pad oxide layer. A nitride layer is deposited overlying the polysilicon layer. Trenches are etched through the nitride layer, polysilicon layer, and pad oxide layer into the silicon semiconductor substrate and filled with an oxide layer. In one alternative, a silicon oxynitride layer is deposited overlying the oxide layer. A first polishing is performed to polish away the silicon oxynitride layer and oxide layer using a first slurry having high selectivity of oxide to nitride. A second polishing is performed to polish away the oxide layer using a second slurry having a low selectivity of oxide to nitride and having low-defect properties.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 11, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Juing-Yi Cheng, Kevin Su
  • Patent number: 6638866
    Abstract: A method of forming shallow trench isolation using CMP is described. A pad oxide layer is grown overlying a silicon semiconductor substrate. A polysilicon layer and a nitride layer are deposited. Trenches are etched through the nitride layer, polysilicon layer, and pad oxide layer into the silicon semiconductor substrate and filled with an oxide layer. A silicon oxynitride layer is deposited overlying the oxide layer. A first polishing is performed to polish away the silicon oxynitride layer and oxide layer using a first slurry having high selectivity of oxide to nitride. A second polishing is performed to polish away the oxide layer using a second slurry having a low selectivity of oxide to nitride. The nitride layer is removed and a third polishing is performed to planarize the oxide layer using a third slurry having high selectivity of oxide to polysilicon.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: October 28, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Juing-Yi Cheng, Kevin Su