Patents by Inventor Kevin T. Campbell

Kevin T. Campbell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8260982
    Abstract: Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 4, 2012
    Assignee: LSI Corporation
    Inventors: Christopher D. Paulson, Timothy D. Thompson, Kevin T. Campbell
  • Patent number: 8151172
    Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 3, 2012
    Assignee: LSI Corporation
    Inventors: Alan D. Poeppelman, Kevin T. Campbell
  • Patent number: 7801184
    Abstract: Disclosed is an adaptive method for training a source synchronous parallel receiver. The adaptive method for training, or aligning, parallel data channels permits a parallel communication receiver to adaptively adjust the timing of data channels to align the data channels with a frame channel and achieve a source synchronous signal for the parallel data channels. Further, portions of the frame channel training pattern may be used because possible time shift accuracy error is accounted for between the communication channels and a determination is made as to which portion of the frame pattern is currently being received. The data channels are then aligned appropriately.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: September 21, 2010
    Assignee: LSI Corporation
    Inventors: Christopher D. Paulson, Timothy D. Thompson, Kevin T. Campbell
  • Publication number: 20100011277
    Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 14, 2010
    Inventors: Alan D. Poeppelman, Kevin T. Campbell
  • Patent number: 7061267
    Abstract: A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: June 13, 2006
    Assignee: LSI Logic Corporation
    Inventors: Kevin T. Campbell, Timothy D. Thompson, Christopher D. Paulson
  • Patent number: 6112452
    Abstract: An insect trap head that can be configured to contain one or two sets of threads to enable the invention to screw onto common household bottles with different opening diameters and different threading alignment and convert these bottles into an insect trap. The insect trap head has a cylindrical top section with an entry opening and a first set of threads being axially orientated to enable the top section to screw onto a bottle with an externally threaded neck. A conical insect entryway section is disposed in the entry opening of the top section. The insect entryway having an entryway skirt section gradually tapering as it projects downwards defining a bottom opening. A ring-shaped bottom section extends peripherally from the top section. The bottom section has a second set of threads that are axially orientated to enable the bottom section to screw onto an alternative bottle requiring a different orientation of threads than that of the first set of threads.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: September 5, 2000
    Inventor: Kevin T. Campbell