Abstract: A computer architecture, hardware modules, and a software method, collectively referred to as “EVISA,” are described that allow low-overhead multithreading program execution to be performed in such a way as to keep all processors usefully busy and satisfy real-time timing constraints. The architecture can be incorporated into the design of a multithreading instruction processor, or can be used as a separate architectural module in conjunction with pre-existing non-multithreading processors as well as specialized Intellectual Property (IP) core modules for embedded applications.