Abstract: Circuits, systems and methods are provided wherein a bypass circuit provides an auxiliary current path to supply current from a power supply line to an electrical load. The bypass circuit is used during a low-power mode, and consumes less quiescent power than a main current path that provides current from the power supply line to the electrical load during normal operation. The bypass circuit includes a current limiter and a comparator, and generates a high-current detection signal responsive to the comparator detecting that a current through the current limiter exceeds a maximum allowed or expected current.

Abstract: Circuits, systems and methods are provided wherein a bypass circuit provides an auxiliary current path to supply current from a power supply line to an electrical load. The bypass circuit is used during a low-power mode, and consumes less quiescent power than a main current path that provides current from the power supply line to the electrical load during normal operation. The bypass circuit includes a current limiter and a comparator, and generates a high-current detection signal responsive to the comparator detecting that a current through the current limiter exceeds a maximum allowed or expected current.

Abstract: A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.

Abstract: A charge pump circuit comprising a plurality of charge pumps connected in parallel, each charge pump receiving a plurality of clock signals, having an output (VCP) that is coupled to the output of the at least one other charge pump, and further comprising a first capacitor that is being charged by a switching circuit receiving the clock signals to charge the first capacitor, a second capacitor coupled in series with the first capacitor, the second capacitor provided between a first terminal (IN) of the charge pump and a second terminal (OUT) of the charge pump, wherein the first terminal (IN) of the charge pump is connected to a second terminal (OUT) of another charge pump and the second terminal (OUT) of the charge pump is connected to the first terminal (IN) of another charge pump.

Abstract: A charge pump circuit comprising a plurality of charge pumps each having their outputs connected in parallel, each charge pump receiving a plurality of clock signals, a clock signal oscillator for providing the plurality of clock signals, the clock signals being out of phase, each charge pump having an output (VCP) that is coupled to the output of the at least one other charge pump, further comprising a first capacitor in each charge pump, the first capacitor being charged by a switching circuit receiving the clock signals to charge the first capacitor to a voltage between a supply voltage and a reference potential, and further comprising a second capacitor coupled in series with the first capacitor, the second capacitor provided between a first terminal (IN) of the charge pump and a second terminal (OUT) of the charge pump, wherein the first terminal (IN) of the charge pump is connected to a second terminal (OUT) of another charge pump and the second terminal (OUT) of the charge pump is connected to the firs

Abstract: A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.

Abstract: A current limiting driver circuit for a semiconductor power switch and a switching device including same. The driver circuit includes a sensing circuit for providing a signal representing the current flowing through the semiconductor power switch, a driver circuit for the power switch, a driver circuit for the sensing circuit. and a comparator circuit having a first input provided by an output of the sensing circuit, a second input provided by a reference signal, and an output provided as a signal input for the first and second driver circuits. A first charge pump provides the supply voltage for the driver circuits, and a second charge pump provides the supply voltage for the comparator, which is higher than the supply voltage for the power switch and the sensing circuit, so that the first and second driver circuits limit the current through the power switch and the sensing circuit even when the output of the sensing circuit approaches the value of the reference signal.