Abstract: A substrate is placed on a charging surface, to which a first voltage is applied. Etch-resistant dry particles are placed in a cup in a nozzle to which a second voltage, less than the first voltage, is applied. A carrier gas is directed through the nozzle, which projects the dry particles out of the nozzle toward the substrate. The particles pick up a charge from the potential applied to the nozzle and are electrostatically attracted to the substrate. The particles adhere to the substrate, where they form an etch mask. The substrate is etched and the particles are removed. Emitter tips for a field emission display may be formed in the substrate.

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract: The present invention is a baseplate that has a supporting substrate with a primary surface upon which an array of emitters is formed. An insulator layer with a plurality of cavities aligned with respective emitters is disposed on the primary surface, and an extraction grid with a plurality of cavity openings aligned with respective emitters is deposited on the insulator layer. The extraction grid is made from a silicon based layer of material. A current control substrate formed from the silicon based layer of material of the extraction grid is provided such that the current control substrate is electrically isolated from the extraction grid and electrically connected to the emitters. The current control substrate has sufficient resistivity to limit the current from the emitters.

Abstract: A cap layer is placed on a substrate of inexpensive glass prior to subsequent processing to form emitter tips. The cap layer substantially reduces shrinkage of the substrate, significantly improves uniform formation of silicon tips, and substantially eliminates delamination of silicon layers from the substrate.

Abstract: The present invention is a baseplate that has a supporting substrate with a primary surface upon which an array of emitters is formed. An insulator layer with a plurality of cavities aligned with respective emitters is disposed on the primary surface, and an extraction grid with a plurality of cavity openings aligned with respective emitters is deposited on the insulator layer. The extraction grid is made from a silicon based layer of material. A current control substrate formed from the silicon based layer of material of the extraction grid is provided such that the current control substrate is electrically isolated from the extraction grid and electrically connected to the emitters. The current control substrate has sufficient resistivity to limit the current from the emitters.

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract: The disclosed polishing apparatus includes a lower pad and an upper pad. The upper pad is disposed over the lower pad and has an upper abrasive surface. The lower pad has an upper surface defining one or more grooves. When the upper pad is placed over the lower pad, channels may form in the upper pad abrasive surface over the grooves. These channels improve the distribution of slurry in the polishing apparatus. The upper pad may define a first polishing region and a second polishing region, the total area of channels in the first polishing region being greater than the total area of the channels in the second polishing region.

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract: A substrate is placed on a charging surface, to which a first voltage is applied. Etch-resistant dry particles are placed in a cup in a nozzle to which a second voltage, less than the first voltage, is applied. A carrier gas is directed through the nozzle, which projects the dry particles out of the nozzle toward the substrate. The particles pick up a charge from the potential applied to the nozzle and are electrostatically attracted to the substrate. The particles adhere to the substrate, where they form an etch mask. The substrate is etched and the particles are removed. Emitter tips for a field emission display may be formed in the substrate.

Abstract: A method for forming semiconductor devices involves defining a pattern of microspheres on a first structure and transferring that pattern of microspheres to a semiconductor structure. The microspheres may then be used as a mask to define features on the semiconductor structure. In this way, it is possible to form semiconductor devices without necessarily using a stepper. This may result in substantial capital savings in semiconductor manufacturing processes.

Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.

Abstract: A micropoint assembly of a field emission device ("FED") including a baseplate, one or more conductors formed over the baseplate, and one or more micropoints formed over the conductor(s) is disclosed. The micropoint assembly further indudes resistive structures associated with specific FED elements that limit current to a maximum level and minimize impact to remaining elements of the device. Any variation in resistivity is uniformly distributed since the same process is consistently applied across a plurality of element locations.

Abstract: A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.

Abstract: An emitter structure for a field emission display includes: a substrate (100) having a top surface; an address line (142) embedded in the substrate (100) and having an upper surface substantially coplanar with the top surface of the substrate (100); and an emitter site (152) having an emitter (154) superjacent to the top surface of the substrate (100) apart from the address line (142) and having a contact (153) having a first portion coupled to the emitter (142) and a second portion coupled to the address line (142). The substrate (100) may further include a base layer (110), and a dielectric layer (120), and the contact (153) may further act as a resistor to limit the current to the emitter (154).

Abstract: A method for use in manufacture of field emitter devices is provided specifically for forming electron emitter tips in a doped semiconductor substrate. The method comprises the following steps: forming a depression around an emitter area in the substrate; doping the substrate in the depression; and expanding the dopant in the depression into the emitter area.

Abstract: Grooves are cut into an under pad of a polishing pad assembly formed by an under pad and an over pad. The grooves cause channeling of the over pad so that slurry received on the polishing face of the pad assembly is delivered across the pad assembly's surface in a controlled fashion.

Abstract: A field emission display includes a substrate (400) having a trench (402) formed therein, an emitter (418) formed in the trench (402), a dielectric layer (412) disposed on the substrate (400), and a grid material layer (406) disposed on the dielectric layer (412). The dielectric layer (412) is exposed by a planarization method. Consequently, the emitter (418) is necessarily aligned with the opening in the grid material layer (406). An electric field applied to the grid material layer (406) activates emitter (418) to emit electrons (416) to strike a faceplate (414).

Abstract: According to the present invention, there is provided a method for forming an emitter grid in a substrate of a field emission display. In one embodiment of the invention, the method includes the step of forming an emitter in a trench in the substrate, the trench having a dimension which is substantially the same as a desired dimension of the emitter grid, disposing a dielectric layer on the substrate, and disposing a grid material layer on the dielectric layer. The field emission display is then planarized to expose a portion of the dielectric which contacts the emitter.

Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.