Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Methods and systems of managing radio based power may include a mobile platform having a plurality of radios and logic to detect changes in location for the mobile platform. The logic may also deactivate at least one of the plurality of radios in response to the changes in location. The changes in location may be detected based on location information obtained from one or more active radios in the plurality of radios and connection losses with respect to active radios in the plurality of radios.

Abstract: Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong “on” state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

Abstract: A system and method for remediating contaminated surfaces in order to reoccupy sites in which such impacted surfaces are contained is disclosed. The systems and methods include forming a first barrier substantially over a surface, the first barrier comprising a first solvent-resistant coating and having a first color, forming a second barrier substantially over the first barrier, the second barrier comprising a second solvent-resistant coating and having a second color, and providing an overlay over the second barrier, the overlay comprising an upper covering, a lower covering and a plurality of support members, wherein each of the plurality of support members have a distal end and proximal end, and the support, members are connected to the upper covering at the distal end, and to the lower covering at the proximal end. Utility lines, telephone line, cable cords, ductwork, etc.

Abstract: Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong “on” state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

Abstract: A method and system are described for sharing a plurality of interrupt inputs associated with a processor among a plurality of interrupt sources. Each of the plurality of interrupt sources is mapped to each of the plurality of interrupt inputs. Interrupt requests from each of the plurality of interrupt sources to one or more of the plurality of interrupt inputs are selectively enabled, e.g., via control bits. The control bits are preferably dynamically modifiable according to user preferences.

Abstract: A Random Access Memory with error detection/correction capability includes an information array (10) for storage of a collective data word in a single row thereof and a parity array (12) for storage of corresponding parity information in a single row thereof. A single row of the information array (10) and the parity array (12) are accessed and input to an error correct circuit (54). The collective data and parity information are also input to an error syndrome/parity generator (48), the output of which is input to the error correct circuit (54) to correct bits that are in error. A latch (72) is provided for latching the corrected information therein to allow new data to be written therein. The output of the latch (72) is multiplexed into the error syndrome/parity generator (48) which is configurable as a parity generator to generate new parity information for a write operation. The new collective data and parity information in the write mode are stored in arrays (10) and (12).

Abstract: A self testing ROM includes an information array (10) for storing data therein and a parity array (12) for storing associated parity information for each of the data words. The data is accessed and multiplexed for input to a block code error detect circuit (30) for detecting the error and outputting an error syndrome on a bus (32). The error syndrome is input to an error correct circuit (34) for correction of the accessed data during a first pass through the error detect circuit (30). This corrected data is then input to latches (39) and (41). The latched data is then input back to the block code error detect circuit (30) during a second pass to determine if the data was corrected. If not, this indicates that there were too many errors to be corrected by the error detection algorithm. This is detected with a system error detect circuit (43) during the second pass through the block code error detect circuit (30).