Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Abstract: Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.

Abstract: A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.

Abstract: A circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifiers to ascertain the values stored by memory cells of the array. The circuit includes a first branch which has transistor circuitry for establishing a reference current, a second branch of the circuit including a first transistor device and apparatus for mirroring the reference current through the first transistor device, and a plurality of output branches each connected to a sense amplifier to provide a reference voltage to be used by the sense amplifier. Each of the output branches includes a second transistor device with characteristics essentially identical to the characteristics of the first transistor device.

Abstract: A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the memory device is in a first output mode. When the control signal is in the second voltage state, the memory device is in a second output mode. Circuitry is provided for selectively coupling the plurality of output pins to the memory array. An output mode select logic is coupled to receive the control signal for selecting the first output mode and the second output mode for the memory device. When the memory device is in the first output mode, the output mode select logic controls the circuitry to couple all of the plurality of output pins to the memory array. When the memory device is in the second output mode, the output mode select logic controls the circuitry to couple a portion of the plurality of output pins to the memory array.

Abstract: In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.

Abstract: A circuit to ensure that a flash memory device with a write state machine ("WSM") and address transition detection ("ATD") provides correct data after a write/erase step, after an erase suspend command is issued or when the device comes out of deep power-down mode. Whenever the WSM takes control of the device the ATD circuits are disabled. When the WSM relinquishes control over the read path it enables ATD by deasserting the disable ATD bar ("DATDB") signal. An internal signal that is a logical inversion of the chip enable bar ("CEB") input is used along with the DATDB signal to generate ATD pulses. Hence, if the user presents a valid address at the address pins with CEB held deasserted when entering the erase suspend mode, the deassertion of the DATDB by the WSM will generate an ATD pulse and valid data will be presented on output pads of the device after an access time.