Abstract: A digital signal processor includes a control circuit for controlling transfer of instructions to and between a computation unit, a memory and an instruction cache. The memory includes a plurality of memory blocks. The control circuit includes a circuit for detecting a memory conflict condition when an instruction address on a first bus and a data address on a second bus both reference locations in one of the memory blocks in a single clock cycle. In response to the memory conflict condition, the instruction corresponding to the instruction address is fetched from the instruction cache when the instruction is stored in the instruction cache. When the instruction is not stored in the instruction cache, the instruction is fetched from memory and is loaded into the instruction cache. An internal memory conflict occurs when the instruction address and the data address reference locations in the same block of internal memory in the same clock cycle.

Abstract: An emulation system used to debug software for a digital signal processor (DSP) includes a built-in digital signal analyzer which operates upon the same digital signals as those presented directly to and outputted by the DSP, bypassing the signal converters used to convert an input analog signal to digital format and the output digital signal to analog format. A host computer communicates with the digital signal analyzer via firmware in a control processor and personality board, or is alternately connected directly with the analyzer. Communications between the digital signal analyzer and the DSP are through the same contact probe as that used for the emulation software. The analyzer may be used to trigger a software function within the emulator based upon the real-time signal from the DSP, and is also capable of interpolating between successive digital values of an analyzed signal for display purposes.

Abstract: The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether it is a program memory data access (PMDA) instruction that requires a data transfer from the program memory when the next instruction is fetched from the program memory. If it is a PMDA instruction, the next instruction is loaded into a cache, which then provides the stored instruction each time the PMDA instruction reappears. This relieves a bottleneck resulting from a simultaneous call for both the next instruction, and datum for the current instruction, from the program memory. The cache is used only for an instruction following a PMDA instruction, and can thus have a substantially smaller capacity than previously.