Patents by Inventor Kevin W. McCauley

Kevin W. McCauley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to improve a testability analysis of a hierarchical design
    Patent number: 6532571
    Abstract: A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard M. Gabrielson, Kevin W. McCauley, Richard F. Rizzolo, Bryan J. Robbins, Joseph M. Swenton