Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.

Abstract: A host interface module is operable to couple the disk drive to a host device. The host interface module includes a plurality of personality modules, each of the plurality of personality modules, when coupled to the host device, is operable to accept read and write commands and transfer data to and from the host device in a corresponding one of a plurality of host interface protocols. A universal host module decodes read and write commands from the host device and transports data written to and read from the disk drive via a first of the plurality of personality modules. A multiplexer selectively couples the first of the plurality of personality modules to the universal host module in response to a selection signal. A system interface couples the universal host module to a processor and a memory of the disk controller.

Abstract: The present invention allows more than two devices to be connected to a single ATA bus. The devices are each assigned a unique identifier, and a controller selects a device by sending a selection command that includes a selection identifier across data lines of the ATA bus to the devices. The devices each receive the selection command and compare the selection identifier to the assigned identifier. The device which matches the selection identifier to its assigned identifier is selected, and the other devices are not selected.

Abstract: An optical disk storage tray having a plurality of storage locations, each of which is supplied with a separate optical head and drive mechanism and with common electronics for controlling the optical heads and drive mechanisms and for interfacing them to a host device.