Abstract: A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.

Abstract: A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.

Abstract: A method and system for generating a set of scan diagnostic patterns for diagnosing fails in scan chains. The method including: (a) selecting a set of latches; (b) selecting a pattern from a set of test patterns; (c) determining the number of lateral insertions of the selected pattern; (d) determining a number of new lateral insertions that the selected pattern would add to the set of scan diagnostic pattern and adding the selected pattern and a corresponding new insertion count to a count list; (e) repeating steps (b) through (d) until all patterns of the set of test patterns have been selected; (f) selecting a pattern from the count list; (g) adding the pattern selected from the count list to the set of scan diagnostic patterns; and (h) repeating steps (b) through (g) until a there are a predetermined number of patterns in the set of scan diagnostic patterns.

Abstract: This invention teaches a computerized method for diagnosing both transient and stuck faults in scan chains. The method first examines repeating patterns in the scan test to determine the type of fault and creates a signature load for each stuck and transient fault based on the pattern for each type of fault. The method then runs a simulation using the signature at a selected assumed fault position. The results of the simulation are then compared with the actual scan result to see if the fault position was determined. If not, the method continues to run simulation on selected assumed fault positions until the simulated result matches the actual scan test results.