Patents by Inventor Kevin Wayne Locker

Kevin Wayne Locker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase lock loop system and method
    Patent number: 6577174
    Abstract: Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: June 10, 2003
    Assignee: Honeywell International Inc.
    Inventors: Kevin Wayne Locker, Joseph Murray
  • Phase lock loop system and method
    Publication number: 20010043098
    Abstract: Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.
    Type: Application
    Filed: July 23, 2001
    Publication date: November 22, 2001
    Inventors: Kevin Wayne Locker, Joseph Murray
  • Phase lock loop system and method
    Patent number: 6297702
    Abstract: Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: October 2, 2001
    Assignee: Honeywell International Inc.
    Inventors: Kevin Wayne Locker, Joseph Murray