Patents by Inventor Kevin Weaver

Kevin Weaver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030061089
    Abstract: The present invention includes a staffing application server and a method therefore that facilitates the placement of short-term staffing personnel to fill short-term staffing job postings. The present invention further may be used to fill long term job assignments. The SAS is coupled to a World Wide Web such as the Internet and allows employers and personnel to enroll. After enrolling, the employers may post short-term or long-term jobs and staffing personnel may post specified work conditions, including shift assignments and corresponding compensation. In particular, the SAS system enables staffing personnel to specify different levels of compensation according to the shift he or she might work.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 27, 2003
    Inventor: Kevin Weaver
  • Patent number: 6518074
    Abstract: An integrated circuit backside preparation process back-thins a die using a dry etch process. A wet etch process decaps the integrated circuit to expose the die. After polishing, the prepared integrated circuit is ready for a backside debug analysis.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 11, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Hiep V. Nguyen, Henry Acedo, Smith J. Johnson, Kevin Weaver
  • Patent number: 6424167
    Abstract: A vibration resistant test module for use with semiconductor device test apparatus that includes a test module top plate, a test module bottom plate and a plurality of spring-and-wire assemblies. The test module top and bottom plates each have a plurality of openings extending between their upper and lower surfaces. Each of the spring-and-wire assemblies includes an electrically conducting wire with a top wire end and a bottom wire end, a top electrically conducting spring connector attached to the top wire end, and a bottom electrically conducting spring connector attached to the bottom wire end. The spring-and-wire assemblies are threaded through separate openings in the test module top and bottom plates such that the top electrically conducting spring connectors extend above the upper surface of the test module top plate, while the bottom electrically conducting spring connectors extend below the lower surface of the test module bottom plate.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: July 23, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Gengying Gao, Kevin Weaver
  • Patent number: 6411111
    Abstract: A testing system comprising an electron beam probe, a photon beam probe, and a device under test (DUT) card holder which is positioned between the electron beam probe and the photon beam probe. A first valve is positioned between the electron beam probe and the DUT. A second valve, located on an opposite side of the DUT from the first valve, is positioned between the photon beam probe and the DUT. The first and second valve operate in cooperation to control the pressure surrounding the DUT card. One embodiment of the invention includes a first test chamber and a second test chamber. The first test chamber includes the area between the first side of the DUT card and the first valve. The second test chamber includes the area between the second side of the DUT card and the second valve. The present invention includes a method for using the test system of the present invention to test both the top and bottom surfaces of a semiconductor device.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: June 25, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Geng Ying Gao, Kevin Weaver
  • Patent number: 6117352
    Abstract: The present invention advantageously provides a method for obtaining access to an integrated circuit chip encapsulated within a device package. The present method involves positioning a masking material, i.e., gasket, adjacent to the heat spreader of the device package. The gasket includes a cavity which is aligned adjacent a portion of the heat spreader directly above the chip. An etchant injection system is then placed against the gasket. A heat spreader etchant is then injected directly into the cavity such that the etchant contacts the exposed surface of the heat spreader. The etchant is supplied to the cavity until a opening is etched vertically through the thickness of the heat spreader. If the heat spreader is composed of copper plated with nickel, it is preferred that the etchant be a solution of 70% nitric acid heated to about 80.degree. C. Formation of the opening through the heat spreader may expose an adhesive layer.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: September 12, 2000
    Assignee: LSI Logic Corporation
    Inventors: Kevin Weaver, Steve E. Scott
  • Patent number: 6100590
    Abstract: A low capacitance multilevel metal interconnect structure for use in integrated circuits that provides for increased IC device speed and that includes a plurality of patterned metal layers separated and supported by an interconnect dielectric material. The low capacitance multilevel metal interconnect structure has interconnect structure related capacitance lowering gaps in the interconnect dielectric material with the gaps, adjoining at least one of the patterned metal layers. While the gaps adjoin at least the uppermost patterned metal layer, they can also extend downward through the interconnect dielectric material such that they also adjoin one or more patterned metal layers that underlie the uppermost patterned metal layer. A process for the manufacture of the low capacitance multilevel metal interconnect structure includes a step of removing interconnect dielectric material from a conventional multilevel metal interconnect structure to form gaps adjoining at least one of the patterned metal layers.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: August 8, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Hengyang James Lin, Kevin Weaver
  • Patent number: 6083848
    Abstract: A method for removing solder from the leads of ICs including immersing the IC in an acid solution. The acid solution dissolves the excess solder on the IC leads. The acid solution is preferably a hydrogen chloride solution containing about 38% hydrogen chloride and 62% water. The acid solution, however, can contain up to 50% hydrogen chloride. After the IC is immersed for a period of time, preferably ten minutes, it is removed from the acid solution and rinsed with water. The IC is rinsed so as to remove any remaining acid solution residue. Rinsing for 5 minutes or more typically ensures removing all of the acid solution. The IC is then inspected to determine whether substantially all of the excess solder is removed from the IC leads. If excess solder still remains on the IC leads, the IC is reintroduced into the solder removing process including immersing the IC in the acid solution, rinsing the IC with water, and inspecting the IC.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: July 4, 2000
    Assignee: LSI Logic Corporation
    Inventors: Emery Sugasawara, Kevin Weaver, Jay Hidy
  • Patent number: 6043100
    Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: March 28, 2000
    Inventors: Kevin Weaver, Terry Barrette
  • Patent number: 5990543
    Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: November 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Kevin Weaver, Terry Barrette