Abstract: A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

Abstract: A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.

Abstract: A resistive network include multiple resistive units; each resistive unit is made up of multiple resistive elements, which can be arranged in a parallel configuration. Each of the resistive elements can be programmable (e.g., switched on or off, or set to one of multiple resistance values). Furthermore, a method of analog computing includes configuring multiple resistive elements in each of multiple resistive units and configuring the resistive units into a network. The configuration of the resistive elements can be, for example, arranging them into a parallel combination. The method further includes programming each resistive unit, for example, by switching individual resistive elements into, or out of, the parallel combination.

Abstract: According to the present invention, a comparison circuit for combining a plurality of data bits is provided. One version of the invention includes a comparator which provides a signal responsive to a comparison of the voltage states of at least two of the plurality of data bits, and an amplifier which is coupled to the comparator and compares the signal provided by the comparator to a reference voltage to provide an output signal, the reference voltage being between a high and a low voltage state.