Abstract: A switching power converter is provided with a one-shot bias boosting circuit that responds to a premature trip point to boost the performance of a linear comparator in a pulse width modulator. In a sense-amplifier based implementation of the comparator, a clock-edge generator boosts the performance of the sense amplifier at the premature trip point.

Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter includes a master switching stage and a slave switching stage that are controlled by a pulse-width-modulation (PWM) controller.

Abstract: A switching power converter is provided with a one-shot bias boosting circuit that responds to a premature trip point to boost the performance of a linear comparator in a pulse width modulator. In a sense-amplifier based implementation of the comparator, a clock-edge generator boosts the performance of the sense amplifier at the premature trip point.

Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

Abstract: A pulse-width-modulated switching power converter is provided in which a comparator has a boosted speed to determine a trip point at which a ramp signal equals an error signal. In a linear comparator embodiment, a one-shot bias boosting circuit triggers an increased bias current to the linear comparator to boost the speed to determine the trip point. In a sense-amplifier-based comparator embodiment, a clock generator enables the sense-amplifier-based comparator prior to the trip point.

Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter includes a master switching stage and a slave switching stage that are controlled by a pulse-width-modulation (PWM) controller.

Abstract: Disclosed is an interleaved buck-boost converter. The interleaved buck-boost converter comprises a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage-level controller. The MLDC converter includes the IMPM and the IMPM includes the flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor and the voltage-level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor and switches a state of operation of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

Abstract: A switched-capacitor converter is provided that includes an intermediate voltage generator having a flying capacitor. A sampling and hold circuit samples a top plate voltage for the flying capacitor and samples a bottom plate voltage for the flying capacitor to form an output voltage for the switched-capacitor converter.

Abstract: A multi-phase switching power converter is disclosed in which the duty cycle of active phases following a phase shedding transition is temporarily adjusted to increase the operating speed of the multi-phase switching power converter.

Abstract: A switched-capacitor converter is provided that includes an intermediate voltage generator having a flying capacitor. A sampling and hold circuit samples a top plate voltage for the flying capacitor and samples a bottom plate voltage for the flying capacitor to form an output voltage for the switched-capacitor converter.

Abstract: A pulse-width-modulated switching power converter is provided in which a comparator has a boosted speed to determine a trip point at which a ramp signal equals an error signal. In a linear comparator embodiment, a one-shot bias boosting circuit triggers an increased bias current to the linear comparator to boost the speed to determine the trip point. In a sense-amplifier-based comparator embodiment, a clock generator enables the sense-amplifier-based comparator prior to the trip point.

Abstract: A multi-phase switching power converter is disclosed in which the duty cycle of active phases following a phase shedding transition is temporarily adjusted to increase the operating speed of the multi-phase switching power converter.

Abstract: A multi-phase switching power converter is disclosed in which the duty cycle of active phases following a phase shedding transition is temporarily adjusted to increase the operating speed of the multi-phase switching power converter.

Abstract: A multi-phase switching power converter is disclosed in which the duty cycle of active phases following a phase shedding transition is temporarily adjusted to increase the operating speed of the multi-phase switching power converter.

Abstract: A two-stage power converter is disclosed in which a second stage may command a first stage to adjust an output voltage from the first stage to compensate for PVT variations in the second stage. Alternatively, the second stage may adjust a clocking frequency to compensate for the PVT variations.

Abstract: Driver circuits with S-shaped gate drive voltage curves for ramp-up and ramp-down of power field effect transistors are presented. In ramp-up, the S-shaped curve rapidly ramps the gate voltage of the power FET to its threshold. This ramp-up is self-terminating. The gate voltage of the power FET is slewed through saturation with a time constant. After a predetermined time, the gate of the power FET is driven to approach the supply voltage level. In ramp-down, the S-shaped curve rapidly ramps the gate voltage of the power FET down to its threshold voltage. This ramp-down is self-terminating. The gate voltage of the power FET is slewed through saturation. The gate-source voltage of the power FET is rapidly ramped down to zero. Such S-shaped curves for the gate drive signal allow the control of the transition times of the gate drive signal to acceptable levels of voltage/current spikes and electromagnetic interference.

Abstract: A multi-phase switching power converter includes a panic mode detector that triggers the activation of each phase in an open-loop mode of operation in which an open-loop duty cycle is used that is greater than a closed-loop duty cycle used during closed-loop operation for the active phases.

Abstract: A two-stage multi-phase switching power converter operates its first stage during nominal operation responsive to a nominal clocking frequency and operates its second stage during the nominal operation responsive to a second-stage clocking frequency that is greater than the nominal clocking frequency. In response to an application of a load, the first stage temporarily increases its clocking frequency from the nominal clocking frequency and implements a fixed duty cycle.

Abstract: In one or more embodiments, a method comprises comparing an output voltage for a multi-phase DC-DC switching power converter to a reference voltage to produce an error voltage. The method further comprises, for a first inductor, generating a first dual-ramp voltage signal having a first DC voltage level, and level-shifting the first dual-ramp voltage signal to form a second dual-ramp voltage signal having a second DC voltage level different from the first DC voltage level. Further, the method comprises switching on a first power switch coupled to the first inductor according to a duty cycle determined responsive to a comparison of the second dual-ramp voltage signal to the error voltage, where the level-shifting of the first dual-ramp voltage signal adjusts the duty cycle of the first power switch to balance a current in the first inductor with a current in a second inductor for the multi-phase DC-DC switching power converter.

Abstract: A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.