Abstract: In examples, a ceramic semiconductor package includes a first semiconductor die; a second semiconductor die; and a ceramic body including a ceramic member. The ceramic member comprises a first conductor on a top surface of the ceramic member and a second conductor. The second conductor includes a first member on the top surface of the ceramic member and separated from the first conductor, the first member coupled to a device side of the first semiconductor die; and a second member coupled to the first member by a vertical member, the second member extending horizontally within the ceramic member parallel to and coinciding vertically with the first conductor, the second member coupled to a device side of the second semiconductor die.

Abstract: A dual-mode positioning driver (32) for a voice coil motor (22) in a disk drive system (10) is disclosed. Linear prestage drivers (38) and pulse-width-modulated prestage drivers (46) are both coupled to power transistors (50) arranged in an “H” bridge for driving the voice coil motor (22). The positioning driver (32) is thus operable to drive the power transistors (50) in either a linear mode or a pulse-width-modulated class D mode. In a transition period while switching from the pulse-width-modulated mode to linear mode, comparators (56H, 56L) compare the phase voltages in the “H” bridge with a reference voltage. The outputs of the comparators (56H, 56L) are applied to the PWM output amplifiers (54H, 54L) to drive the power transistors (50), so that the phase voltages are preconditioned toward their linear bias points. Discontinuities in the drive current through the voice coil motor (22) are minimized as a result.

Abstract: A positioning driver (32) for a voice coil motor (22) in a disk drive system (10) is disclosed. Pulse-width-modulated prestage drivers (46) are coupled to power transistors (50) arranged in an “H” bridge for driving the voice coil motor (22), biased with a power supply voltage (VM). The pulse-width-modulated prestage drivers (46) drive the power transistors (50) according to a comparison between an error signal from an error amplifier (36) and a ramp clock signal (RMP) generated by a ramp clock generator (46). The ramp clock generator (46) includes a control circuit (68) that modulates the high and low limits of the ramp clock signal (RMP) in response to variations in the power supply voltage (VM). This modulation of the high and low limits compensates for variations in the gain of the power transistors (50) resulting from variations in the power supply voltage (VM).