Patents by Inventor Kewal Saluja

Kewal Saluja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9960910
    Abstract: A system for creating protected functional descriptions of integrated circuits provides encrypted gate delay information preventing deduction of gate function from gate delay but allowing simulation of the integrated circuit with accurate propagation delay calculation. Individual gate delay values may be modified so that they obscure actual gate delays but so that the modified individual gate delays total to equal the actual cumulative gate delay along a given data propagation path.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 1, 2018
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Parameswaran Ramanathan, Kewal Saluja
  • Publication number: 20170250800
    Abstract: A system for creating protected functional descriptions of integrated circuits provides encrypted gate delay information preventing deduction of gate function from gate delay but allowing simulation of the integrated circuit with accurate propagation delay calculation. Individual gate delay values may be modified so that they obscure actual gate delays but total along a data propagation path to equal the actual cumulative gate delay along that data propagation path.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Parameswaran Ramanathan, Kewal Saluja
  • Patent number: 9390292
    Abstract: A system for creating protected functional descriptions of integrated circuits provides an encrypted functional description that allows the integrated circuit to be simulated with respect to producing outputs for given sets of inputs without identification of the constituent components of the integrated circuit such as the logical gates making up the integrated circuit. The encrypted functional description may include encrypted truth-tables describing the generic gates of the integrated circuit, the encrypted truth-tables securing the function of each logical gate by including multiple redundant table entries mapped to alias values of Boolean logical states and erroneous table entries.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 12, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Spencer Millican, Parameswaran Ramanathan, Kewal Saluja
  • Publication number: 20150188661
    Abstract: A system for creating protected functional descriptions of integrated circuits provides an encrypted functional description that allows the integrated circuit to be simulated with respect to producing outputs for given sets of inputs without identification of the constituent components of the integrated circuit such as the logical gates making up the integrated circuit. The encrypted functional description may include encrypted truth-tables describing the generic gates of the integrated circuit, the encrypted truth-tables securing the function of each logical gate by including multiple redundant table entries mapped to alias values of Boolean logical states and erroneous table entries.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Spencer Millican, Parameswaran Ramanathan, Kewal Saluja