Abstract: Provided are devices and methods for transmitting two or more data streams through the same cable. An exemplary cable includes at least two sets of conductive points, each set capable of independently transmitting a separate data stream. The cable may be a USB 2.0 type cable, with two contacts assigned for transmitting one data stream, and two other contacts assigned for transmitting another data stream. In some embodiments, one data stream is an audio-video signal transmitted to an audio-video receiver.

Abstract: Provided are methods for transmitting two or more data streams through the same cable. The cable includes at least two sets of conductive points, each set capable of independently transmitting a separate data stream. The cable may be USB 2.0 type cable. Pins 2 and 3 may be assigned for transmitting one data stream, while pins 4 and 5 may be assigned for transmitting another data stream. For example, one data stream may be audio-video signal transmitted to an audio-video receiver.

Abstract: Embodiments include systems and methods of powering data communications transmitter circuitry using current sinked from biasing circuitry used to bias a transmission line between the data communications transmitter circuitry and data communications receiver circuitry. In some embodiments, the current sinked from the biasing circuitry is sourced by a power supply configured to power the data communications receiver circuitry. The current sinked from the biasing circuitry is then re-used to power the data communications transmitter circuitry. The data communications transmitter circuitry can be operated using less power overall than the prior art by re-using the current first used to bias the transmission line to power the data communications transmitter circuitry. Various embodiments include HDMI transceivers, DVI transceivers, and DisplayPort transceivers.

Abstract: Signaling and coding methods and apparatus for long-range 10 and 100 mbps Ethernet transmission. In accordance with the method, a physical layer (PHY) device is provided that includes the long-range capabilities. In operation, the PHY measures the distance to a companion PHY, and if it is within the specification limits, communicates with the companion device in the normal way. If the distance is above the specification limits, the PHY checks to see if the companion PHY is similarly enabled, and if so, switches to a long-range signaling method. In a preferred embodiment, NRZ coding with pre-emphasis on the first bit of two or more bits of the same value is used for a first range exceeding the specification limit, and PAM4 coding is used for a second range exceeding the first range. Various embodiments are disclosed.

Abstract: Incoming bit stream is processed by a single state machine into a circular buffer. Circular buffer accumulates subunits of data to form a major data unit. State machine recognizes the start of major data unit and flags the location of the major data unit in the circular buffer.

Abstract: Optical transducers disposed on an integrated circuit correspond to test points thereon. The state of optical transducers perceived by an optical sensor is correlated to test points. Alignment of the optical sensor relative to the optical transducers is accomplished electronically or mechanically.

Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.

Abstract: Signaling and coding methods and apparatus for long-range 10 and 100 mbps Ethernet transmission. In accordance with the method, a physical layer (PHY) device is provided that includes the long-range capabilities. In operation, the PHY measures the distance to a companion PHY, and if it is within the specification limits, communicates with the companion device in the normal way. If the distance is above the specification limits, the PHY checks to see if the companion PHY is similarly enabled, and if so, switches to a long-range signaling method. In a preferred embodiment, NRZ coding with pre-emphasis on the first bit of two or more bits of the same value is used for a first range exceeding the specification limit, and PAM4 coding is used for a second range exceeding the first range. Various embodiments are disclosed.

Abstract: State of test points on an integrated circuit are encapsulated in a telemetry frame that is wirelessly conveyed to a test system. Test points may be logic levels or analog levels converted into representative multi-bit values. Conveyance off the circuit may be by radio frequency or optical emission.

Abstract: Optical transducers disposed on an integrated circuit correspond to test points thereon. The state of optical transducers perceived by an optical sensor is correlated to test points. Alignment of the optical sensor relative to the optical transducers is accomplished electronically or mechanically.

Abstract: State of test points on an integrated circuit are encapsulated in a telemetry frame that is wirelessly conveyed to a test system. Test points may be logic levels or analog levels converted into representative multi-bit values. Conveyance off the circuit may be by radio frequency or optical emission.

Abstract: Incoming bit stream is processed by a single state machine into a circular buffer. Circular buffer accumulates subunits of data to form a major data unit. State machine recognizes the start of major data unit and flags the location of the major data unit in the circular buffer.

Abstract: Method and apparatus for receiving bus signals from a first computer module, converting those bus signals into a first point-to-point link and directing the first point-to-point link to a bus emulator. The bus emulator propagates data transfer cycles arriving by the first point-to-point link to a second point-to-point link. The second point-to-point link carries data transfer cycles to a second computer module. The second point-to-point link is converted back into bus signals that interface with the second computer module.

Abstract: Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits.

Abstract: In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1.6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases without reference to the word boundaries of data being transmitted. These 16 unreferenced phases are input to a phase rotator that, via a series of calibration steps, maps the unreferenced phases into named phases, and in doing so references the phases to the word boundary of the data being transmitted over the slowest data line of the parallel channel. The named phases are then input to a data interpolator in each receiver, which generates 16 local phases. The 16 local phases correspond to the data-bit centers and data-bit edges for each of the 8 bits transferred per major channel clock period.

Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.