Abstract: Embodiments of the present technology provide a memory die that estimates ICC peak using cost effective (and small area) on-memory die components and processing circuitry. The memory die leverages a temperature sensor to estimate a temperature rise for a substrate region of the memory die located proximate to a wordline ramp up pump during a wordline ramp up process performed before a read operation. Based on the estimated temperature rise for the substrate region, the memory die can determine that an ICC peak of the memory die deviates from a target ICC peak value—and adjust parameters of the wordline ramp up process in a manner that brings the ICC peak of the memory die closer to the target ICC peak value.

Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of nonvolatile memory cells. The control circuits are configured to count a number of pulses sent to switches of a charge pump, record a count of the number of pulses sent to the switches and send the count of the number of pulses in response to a request for the count of the recorded number of pulses.

Abstract: Embodiments of the present technology provide a memory die that estimates ICC peak using cost effective (and small area) on-memory die components and processing circuitry. The memory die leverages a temperature sensor to estimate a temperature rise for a substrate region of the memory die located proximate to a wordline ramp up pump during a wordline ramp up process performed before a read operation. Based on the estimated temperature rise for the substrate region, the memory die can determine that an ICC peak of the memory die deviates from a target ICC peak value—and adjust parameters of the wordline ramp up process in a manner that brings the ICC peak of the memory die closer to the target ICC peak value.

Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide multiple channel-to-gate voltages. Current consumption and time are saved compared to applying a multi-level erase voltage to a high capacitance substrate, for example. In one approach, the word line voltage is changed from a positive erase-enable voltage to a negative erase-enable voltage during the multi-level erase pulse. A step size of a next erase pulse can be set to achieve an approximately constant step increase in channel-to-gate voltages of the memory cells.

Abstract: Techniques and apparatuses are provided for determining the efficiency of a charge pump. A charge pump is driven during a measurement period without limiting its input current. The driving can include ramping up the output of the charge pump from an initial level to a final level and maintaining the output at the final level. A counter counts a number of clock pulses provided to the charge pump during the measurement period. Using a current mirror which limits the input current, a ratio of the current mirror is determined which results in a similar number of clock pulses during the measurement period. The ratio indicates an efficiency of the charge pump and can be used to set control parameters such as ramp up rate and clock frequency.