Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Abstract: An integrated circuit (IC) cell including: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in a cell row direction; and a source region, common to the first and second logic gates, situated between the first and second polysilicon structures, wherein the first and second pins are on a first metal track directly over the common source region.

Abstract: In certain aspects, a chip includes first source/drain contacts formed over a first oxide diffusion (OD), and first gates, wherein each of the first gates is disposed between a respective pair of the first source/drain contacts. The chip also includes a first bridge coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts. The chip also includes a first metal routing coupled to the first one of the first source/drain contacts, and a second metal routing coupled to the second one of the first source/drain contacts.

Abstract: A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

Abstract: A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.