Patents by Inventor Keyvan Kashefizadeh
Keyvan Kashefizadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11462411Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: GrantFiled: April 28, 2021Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter, Dong Wu
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Patent number: 11114320Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.Type: GrantFiled: November 21, 2019Date of Patent: September 7, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Takashi Kuratomi, Avgerinos V. Gelatos, Xianmin Tang, Sanjay Natarajan, Keyvan Kashefizadeh, Zhebo Chen, Jianxin Lei, Shashank Sharma
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Publication number: 20210249270Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Inventors: Gaurav THAREJA, Keyvan KASHEFIZADEH, Xikun WANG, Anchuan WANG, Sanjay NATARAJAN, Sean M. SEUTTER, Dong WU
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Patent number: 11004687Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: GrantFiled: June 17, 2019Date of Patent: May 11, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter, Dong Wu
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Publication number: 20200258744Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: ApplicationFiled: June 17, 2019Publication date: August 13, 2020Inventors: Gaurav THAREJA, Keyvan KASHEFIZADEH, Xikun WANG, Anchuan WANG, Sanjay NATARAJAN, Sean M. SEUTTER, Dong Wu
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Publication number: 20200203481Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.Type: ApplicationFiled: November 21, 2019Publication date: June 25, 2020Inventors: Gaurav THAREJA, Takashi KURATOMI, Avgerinos V. GELATOS, Xianmin TANG, Sanjay NATARAJAN, Keyvan KASHEFIZADEH, Zhebo CHEN, Jianxin LEI, Shashank SHARMA
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Publication number: 20180144973Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 ? to about 60 ?.Type: ApplicationFiled: November 1, 2017Publication date: May 24, 2018Inventors: Weifeng Ye, Jiang Lu, Feng Chen, Zhiyuan Wu, Kai Wu, Vikash Banthia, He Ren, Sang Ho Yu, Mei Chang, Feiyue Ma, Yu Lei, Keyvan Kashefizadeh, Kevin Moraes, Paul F. Ma, Hua Ai
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Patent number: 8168543Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.Type: GrantFiled: September 18, 2009Date of Patent: May 1, 2012Assignee: Applied Materials, Inc.Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
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Patent number: 7846824Abstract: Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate.Type: GrantFiled: March 18, 2008Date of Patent: December 7, 2010Assignee: Applied Materials, Inc.Inventors: Keyvan Kashefizadeh, Zhigang Xie, Ashish S. Bodke, Mei Chang
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Publication number: 20100006425Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
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Patent number: 7618893Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.Type: GrantFiled: March 4, 2008Date of Patent: November 17, 2009Assignee: Applied Materials, Inc.Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
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Publication number: 20090239378Abstract: Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Applicant: APPLIED MATERIALS, INC.Inventors: KEYVAN KASHEFIZADEH, Zhigang Xie, Ashish S. Bodke, Mei Chang
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Publication number: 20090227105Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD processing chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.Type: ApplicationFiled: March 4, 2008Publication date: September 10, 2009Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim