Patents by Inventor Kezhou Xie

Kezhou Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structures and methods for fabricating vertically integrated HBT-FET device
    Patent number: 7718486
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 18, 2010
    Assignee: Anadigics, Inc.
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Structures and methods for fabricating vertically integrated HBT-FET device
    Publication number: 20060113566
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Structures and methods for fabricating vertically integrated HBT/FET device
    Patent number: 7015519
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: March 21, 2006
    Assignee: Anadigics, Inc.
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Monolithically fabricated HBT amplification stage with current limiting FET
    Patent number: 6998920
    Abstract: A monolithically integrated amplifier comprising at least one heterojunction bipolar transistor and at least one field effect transistor is disclosed wherein the field effect transistor provides improved ruggedness by limiting the base and/or collector current to the HBT during severe load mismatch and/or high overdrive.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: February 14, 2006
    Assignee: Anadigics Inc.
    Inventors: Oleh B. Krutko, Aditya K. Gupta, M. Ali Khatibzadeh, Kezhou Xie
  • Structures and methods for fabricating integrated HBT/FET's at competitive cost
    Publication number: 20050184310
    Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
  • Monolithically fabricated HBT amplification stage with current limiting FET
    Publication number: 20050184808
    Abstract: A monolithically integrated amplifier comprising at least one heterojunction bipolar transistor and at least one field effect transistor is disclosed wherein the field effect transistor provides improved ruggedness by limiting the base and/or collector current to the HBT during severe load mismatch and/or high overdrive.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 25, 2005
    Inventors: Oleh Krutko, Aditya Gupta, M. Khatibzadeh, Kezhou Xie
  • Low defect density gallium nitride epilayer and method of preparing the same
    Patent number: 6180270
    Abstract: A GaN epilayaer grown on a lattice mismatched saphire substrate is subjected to rapid thermal processing in order the reduce the defect density especially in the proximate the top (device) surface of the GaN epilayer.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: January 30, 2001
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Melanie Cole, Kezhou Xie