Abstract: Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.

Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.