Abstract: Techniques for performing efficient automatic test-pattern generation (ATPG) are disclosed. ATPG may be performed by ATPG workers whose fault states are synchronized by an ATPG manager. In some embodiments, test-pattern generation by a ATPG worker may be performed multiple times with minimal idle time between generation and fault simulation intervals. Synchronization schemes may be synchronous or asynchronous. In asynchronous schemes, an ATPG worker may determine staleness of its fault state. If the fault state is stale, the ATPG worker may poll the ATPG manager to update the fault state to the current fault state of the ATPG manager which includes information on faults detected (including duplicate faults) by other ATPG workers. In synchronous schemes, fault states may be synchronized without polling by the ATPG worker. The synchronization of fault states via communication between manager and workers may reduce duplication and idle time, hence improving the time efficiency of ATPG workers.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.

Abstract: A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus comprises two or more decompressors embedded between N compressed scan inputs and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows us to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. The method and apparatus further comprises two or more compressors separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.

Abstract: A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network.

Abstract: A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.