Patents by Inventor Khai Leong Yong

Khai Leong Yong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802957
    Abstract: A control module for a multi-level data storage device having a plurality of memory devices is disclosed. The control module may include: an access determination circuit configured to determine that access has been made to a piece of data stored on at least one of the plurality of memory devices, the piece of data associated with a level being one of a first level, a second level, or a third level; a level management circuit configured to change the level from the third level to the second level or from the second level to the first level upon determining that access has been made to the piece of data; and a memory controller configured to promote the piece of data in response to whether the level is the first level, the second level or the third level, wherein at least two levels of the first level, the second level, and the third level are associated with one of the plurality of memory devices.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 13, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Chao Jin, Weiya Xi, Khai Leong Yong
  • Patent number: 10353787
    Abstract: A method for data stripping, allocation and reconstruction in an active drive storage system including a plurality of active object storage devices, each of the plurality of active object storage devices including one or more storage devices and a controller is provided. The method includes the controller of the identified one of the plurality of active object storage devices segmenting the received data into a plurality of data chunks and generating one or more parity chunks in response to the plurality of data chunks. The method further includes the controller of the identified one of the plurality of active object storage devices reorganizing the plurality of data chunks and the one or more parity chunks in response to a number of the plurality of data chunks and a number of the one or more of the plurality of active object storage devices into which the received data is to be stored.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 16, 2019
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND SCIENCE
    Inventors: Chao Jin, Shibin Chen, Weiya Xi, Khai Leong Yong, Quanqing Xu
  • Publication number: 20190102288
    Abstract: A control module for a multi-level data storage device having a plurality of memory devices is disclosed. The control module may include: an access determination circuit configured to determine that access has been made to a piece of data stored on at least one of the plurality of memory devices, the piece of data associated with a level being one of a first level, a second level, or a third level; a level management circuit configured to change the level from the third level to the second level or from the second level to the first level upon determining that access has been made to the piece of data; and a memory controller configured to promote the piece of data in response to whether the level is the first level, the second level or the third level, wherein at least two levels of the first level, the second level, and the third level are associated with one of the plurality of memory devices.
    Type: Application
    Filed: March 15, 2017
    Publication date: April 4, 2019
    Inventors: Chao JIN, Weiya XI, Khai Leong YONG
  • Patent number: 10122381
    Abstract: A method for defining an erasure code for system having a predetermined number of data disks is disclosed. The method includes selecting step, constructing step, determining step and repeating step. The selecting step includes selecting a predetermined acceptable number of failures for the system. The constructing step includes constructing a first Tanner graph for two failures acceptable system having predetermined number of data disks. The determining step includes determining erasure code from the first Tanner graph. The repeating step includes repeating the constructing step and the determining step by increasing the acceptable number of failures by one and constructing another Tanner graph in response to the increased acceptable number of failures by increasing number of parity nodes until the predetermined number of failures for the system is reached.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 6, 2018
    Assignee: Agency for Science, Technology and Research
    Inventors: Chao Jin, Weiya Xi, Khai Leong Yong, Shibin Chen
  • Publication number: 20180246793
    Abstract: A method for data stripping, allocation and reconstruction in an active drive storage system including a plurality of active object storage devices, each of the plurality of active object storage devices including one or more storage devices and a controller is provided. The method includes the controller of the identified one of the plurality of active object storage devices segmenting the received data into a plurality of data chunks and generating one or more parity chunks in response to the plurality of data chunks. The method further includes the controller of the identified one of the plurality of active object storage devices reorganizing the plurality of data chunks and the one or more parity chunks in response to a number of the plurality of data chunks and a number of the one or more of the plurality of active object storage devices into which the received data is to be stored.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 30, 2018
    Inventors: Chao JIN, Shibin CHEN, Weiya XI, Khai Leong YONG, Quanqing XU
  • Patent number: 10061704
    Abstract: A data storage device includes a data storage medium having a plurality of data blocks. A cache includes a plurality of cache blocks. Each cache block includes a corresponding cache block address. A metadata table includes a plurality of table entries for the data blocks, respectively. Each of the table entries is configured to store the cache block address of one of the cache blocks in which data of a corresponding one of the data blocks is written. A bitmap is configured to store statuses of all of the cache blocks, respectively.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Marvell International LTD.
    Inventors: Weiya Xi, Chao Jin, Khai Leong Yong, Sophia Tan, Zhi Yong Ching
  • Publication number: 20180217906
    Abstract: A method for data reconstruction when one HOSD has failed in a cluster of Hybrid Object Storage Devices (HOSDs) is disclosed. The method includes receiving one of a read request and a write request from a server to access data from a failed one of the plurality of storage devices and reconstructing the requested data stored in the failed one of the plurality of storage devices from portions of data stored in one or more available ones of the plurality of storage devices. The method also includes sending the requested data from the reconstructed data back to the server and sending the reconstructed data to a replacement one of the plurality of storage devices. Finally, the method includes updating a reconstruction list to indicate the replacement one of the plurality of storage devices and completion of data reconstruction.
    Type: Application
    Filed: September 30, 2015
    Publication date: August 2, 2018
    Inventors: Chao JIN, Khai Leong YONG, Weiya XI
  • Publication number: 20180107601
    Abstract: A method for data storage in a hybrid storage node of a data storage system is provided. The hybrid storage node includes first and second storage devices having different performance characteristics wherein the first devices includes at least one high performance non-volatile memory for cache storage. The hybrid storage node further includes processing resources for managing data storage in the hybrid storage node. The method includes receiving a read request to read stored information from the hybrid storage node and, in response to the read request, accessing both the cache storage first storage devices and storage in the second storage devices to locate the stored information.
    Type: Application
    Filed: May 20, 2016
    Publication date: April 19, 2018
    Inventors: Chao Jin, Weiya Xi, Khai Leong Yong, Zhi Yong Ching
  • Publication number: 20170277477
    Abstract: An active storage system is disclosed. The active storage system includes a storage device, a non-volatile memory and an active drive controller. The active drive controller performs data management and/or cluster management within the active storage system, the active drive controller including a data interface for receiving at least object and/or file data.
    Type: Application
    Filed: October 2, 2015
    Publication date: September 28, 2017
    Inventors: Weiya XI, Chao JIN, Khai Leong YONG, Pantelis ALEXOPOULOS
  • Publication number: 20170277447
    Abstract: A printed circuit board assembly (PCBA) for a storage device comprising a non-volatile memory (NVM) and a multi-core processor, wherein a first core of the multi-core processor is devoted to external interface management and a second core of the multi-core processor is devoted to internal data management.
    Type: Application
    Filed: September 28, 2015
    Publication date: September 28, 2017
    Inventors: Weiya XI, Chao JIN, Khai Leong YONG, Pantelis ALEXOPOULOS
  • Publication number: 20170279462
    Abstract: A method for defining an erasure code for system having a predetermined number of data disks is disclosed. The method includes selecting step, constructing step, determining step and repeating step. The selecting step includes selecting a predetermined acceptable number of failures for the system. The constructing step includes constructing a first Tanner graph for two failures acceptable system having predetermined number of data disks. The determining step includes determining erasure code from the first Tanner graph. The repeating step includes repeating the constructing step and the determining step by increasing the acceptable number of failures by one and constructing another Tanner graph in response to the increased acceptable number of failures by increasing number of parity nodes until the predetermined number of failures for the system is reached.
    Type: Application
    Filed: September 29, 2015
    Publication date: September 28, 2017
    Applicant: Agency for Science, Technology and Research
    Inventors: Chao JIN, Weiya XI, Khai Leong YONG, Shibin CHEN
  • Publication number: 20170270044
    Abstract: An active storage unit and an active storage array are provided. The active storage unit includes an active control board having a processor, at least one internal memory module communicatively coupled to the processor, and a reconfigurable logic circuit communicatively coupled to the processor for programming the active storage unit. The active storage unit also includes a plurality of storage devices communicatively coupled to the active control board.
    Type: Application
    Filed: October 2, 2015
    Publication date: September 21, 2017
    Inventors: Hong YANG, Khai Leong YONG, Dee Meng KANG
  • Publication number: 20170075809
    Abstract: A data storage device includes a data storage medium having a plurality of data blocks. A cache includes a plurality of cache blocks. Each cache block includes a corresponding cache block address. A metadata table includes a plurality of table entries for the data blocks, respectively. Each of the table entries is configured to store the cache block address of one of the cache blocks in which data of a corresponding one of the data blocks is written. A bitmap is configured to store statuses of all of the cache blocks, respectively.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Weiya XI, Chao JIN, Khai Leong YONG, Sophia TAN, Zhi Yong CHING
  • Patent number: 9524238
    Abstract: A data storage device includes a data storage medium, a cache, and a cache control memory. The data storage medium has M data blocks. M is an integer greater than 1. The cache includes N cache blocks having N cache block addresses, respectively. N is an integer greater than 1. The cache control memory includes M memory elements corresponding to the M data blocks, respectively. The cache control memory is configured to, in response to a request to cache data of one of the M data blocks: (a) write the data from the one of the M data blocks to one of the N cache blocks; and (b) write, in the one of the M memory elements corresponding to the one of the M data blocks, one of the N cache block addresses corresponding to the one of the N cache blocks where the data is written.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 20, 2016
    Assignee: Marvell International LTD.
    Inventors: Weiya Xi, Chao Jin, Khai Leong Yong, Sophia Tan, Zhi Yong Ching
  • Publication number: 20160217040
    Abstract: Data reconstruction in a RAID storage system, by determining if a parity stripe has been reconstructed and if the parity stripe has been allocated, by the checking of a reconstruction/rebuild table and a space allocation table. Before reconstruction of a parity stripe occurs, the non-volatile memory of a failed hybrid drive is checked to determine if it is accessible and if so the data is copied to the new hybrid drive instead of reconstruction occurring.
    Type: Application
    Filed: August 27, 2014
    Publication date: July 28, 2016
    Applicant: Agency for Science, Technology and Research
    Inventors: Chao JIN, Weiya XI, Khai Leong YONG, Zhi Yong CHING, Feng HUO
  • Publication number: 20160170879
    Abstract: A data storage device includes a data storage medium, a cache, and a cache control memory. The data storage medium has M data blocks. M is an integer greater than 1. The cache includes N cache blocks having N cache block addresses, respectively. N is an integer greater than 1. The cache control memory includes M memory elements corresponding to the M data blocks, respectively. The cache control memory is configured to, in response to a request to cache data of one of the M data blocks: (a) write the data from the one of the M data blocks to one of the N cache blocks; and (b) write, in the one of the M memory elements corresponding to the one of the M data blocks, one of the N cache block addresses corresponding to the one of the N cache blocks where the data is written.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventors: Weiya XI, Chao JIN, Khai Leong YONG, Sophia TAN, Zhi Yong CHING
  • Patent number: 9368130
    Abstract: In various embodiments, a data storage system may be provided. The data storage system may include a storage. The storage may include a first portion and a second portion. The data storage system may further include a determination circuit configured to determine whether to write data to the first portion or to the second portion. The data storage system may also include a control circuit configured to control writing the data to the first portion in a log structured manner.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 14, 2016
    Assignee: Marvell International Ltd.
    Inventors: Chao Jin, Weiya Xi, Khai Leong Yong, Zhi Yong Ching
  • Patent number: 9268705
    Abstract: A data storage device is provided. The data storage device includes a data storage medium having a plurality of data blocks, a cache having a plurality of cache blocks, wherein each cache block is identified by a cache block address, a cache control memory including a memory element for each data block configured to store the cache block address of the cache block in which data of the data block is written.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Marvell International LTD.
    Inventors: Weiya Xi, Chao Jin, Khai Leong Yong, Sophia Tan, Zhi Yong Ching
  • Patent number: 9268709
    Abstract: According to various embodiments, a storage controller configured to control storage of data in a pre-determined area of a storage medium may be provided. The storage controller may include a memory configured to store a write pointer, a reclaim pointer, and a wrapped around pointer. The write pointer may indicate a location of the storage medium to write incoming data. The reclaim pointer may indicate a location of the storage medium to perform a space reclamation. The wrapped around pointer may indicate a location of the storage medium where writing is to continue if writing of data reaches an end of the pre-determined area.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 23, 2016
    Assignee: Marvell International LTD.
    Inventors: Weiya Xi, Sufui Sophia Tan, Khai Leong Yong, Chun Teck Lim, Chao Jin, Zhi Yong Ching
  • Patent number: 9202512
    Abstract: According to an embodiment of the present invention, a data storage device comprising a motor having a stator is disclosed. The stator may include a substrate having a first surface and a second surface opposite to the first surface; and a n-phase winding arrangement having n phase windings; wherein each phase winding comprises m flat fractional-pitch coils arranged on the first surface of the substrate such that the coils are spaced apart uniformly along a closed loop and connected in series; wherein each coil together with an angular section of the substrate between the coil and an adjacent coil of the same phase winding defines a stator pole-pair; and wherein m is an integer larger than 1.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: December 1, 2015
    Assignee: Marvell International LTD.
    Inventors: Chao Bi, Kui Cai, Kheong Sann Chan, Zhi Yong Ching, Moulay Rachid Elidrissi, Guchang Han, Zhimin He, Phyu Hla Nu, Jiang Feng Hu, Wei Hua, Quan Jiang, Siang Huei Leong, Wuzhong Lin, Bo Liu, Yansheng Ma, Chun Lian Ong, Jianzhong Shi, Cheng Su Soh, Sufui Sophia Tan, Li Wang, Chiew Leong Wong, Weiya Xi, Khai Leong Yong, Shengkai Yu, Yin Quan Yu, Zhimin Yuan, Jing Liang Zhang, Tiejun Zhou, Pantelis Alexopoulos, Budi Santoso, Qide Zhang, Kannan Sundaravadivelu, Ningyu Liu, Jianqiang Mou, Chong Wee Lee, Ke Gan, Boon Long Ibrahim See, Leonard Gonzaga, Wee Kiat Lim, Mengjun Liu, Venkataramanan Venkatakrishnan, Cheng Peng Tan