Abstract: Disclosed are thiadiazine compounds, derivatives and compositions thereof. The compounds, derivatives, and compositions can be used for treating or preventing a heat-shock protein responsive disorder or suppressing protein aggregation in a subject. The compounds and compositions can also be used for treating cancer, neurodegenerative disorders, and other heat-shock protein responsive disorders.

Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.

Abstract: Aspects of the disclosure provide a power circuit that includes a first switch circuit in parallel with a second switch circuit. The first switch circuit and the second switch circuit are coupled to a first control node, a second control node, a first power node and a second power node via interconnections. The power circuit receives a control signal between the first control node and the second control node to control a current flowing from the first power node to the second power node through the first switch circuit and the second switch circuit. At least one of a first source terminal of the first switch circuit and a second source terminal of the second switch circuit is coupled to the second control node with a resistive element having a specific resistance.

Abstract: A power circuit includes a power source for providing electrical power and two driving transistors being disposed in parallel and receiving electrical power from the power source. Each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection. The power circuit also includes a control voltage source having a first terminal and a second terminal. The control voltage source provides a control signal to the two driving transistors for determining driving currents through the two driving transistors. The first terminal is connected to the gate terminals of the two driving transistors, and the second terminal is connected to the kelvin source connections of the two driving transistors. The kelvin source connections of the two driving transistors are inductively coupled.

Abstract: Aspects of the disclosure provide a power circuit that includes a first switch circuit in parallel with a second switch circuit. The first switch circuit and the second switch circuit are coupled to a first control node, a second control node, a first power node and a second power node via interconnections. The power circuit receives a control signal between the first control node and the second control node to control a current flowing from the first power node to the second power node through the first switch circuit and the second switch circuit. At least one of a first source terminal of the first switch circuit and a second source terminal of the second switch circuit is coupled to the second control node with a resistive element having a specific resistance.

Abstract: Capacitors connected between gate terminals of a plurality of parallel-connected power transistors are charged and discharged in each switching cycle to provide a plurality of power transistor control waveforms from a single gate driver waveform that equalize power losses/temperatures or steady-state currents among the plurality of power transistors. The capacitors are charged to different voltages by diverting current from one transistor driver by disabling another power transistor driver at different respective times in response to measured transient or steady state current or temperature or other operational parameter.

Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.

Abstract: Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.

Abstract: A power circuit includes a power source for providing electrical power and two driving transistors being disposed in parallel and receiving electrical power from the power source. Each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection. The power circuit also includes a control voltage source having a first terminal and a second terminal. The control voltage source provides a control signal to the two driving transistors for determining driving currents through the two driving transistors. The first terminal is connected to the gate terminals of the two driving transistors, and the second terminal is connected to the kelvin source connections of the two driving transistors. The kelvin source connections of the two driving transistors are inductively coupled.

Abstract: Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.

Abstract: Capacitors connected between gate terminals of a plurality of parallel-connected power transistors are charged and discharged in each switching cycle to provide a plurality of power transistor control waveforms from a single gate driver waveform that equalize power losses/temperatures or steady-state currents among the plurality of power transistors. The capacitors are charged to different voltages by diverting current from one transistor driver by disabling another power transistor driver at different respective times in response to measured transient or steady state current or temperature or other operational parameter.

Abstract: Aspects of the disclosure provide a power device that includes an upper power module and a lower power module. The upper power module and the lower power module are coupled in series between two supply voltages, and are respectively controlled by a first control signal and a second control signal. Interconnections of the power device are inductively coupled to prevent reliability issues, such as crosstalk, self turn on, self sustained oscillation, and the like.

Abstract: Aspects of the disclosure provide a power circuit that includes a first switch circuit in parallel with a second switch circuit. The first switch circuit and the second switch circuit are coupled to a first driving node, a second driving node, a source node and a drain node via interconnections. The power circuit receives a control signal between the first driving node and the second driving node to control a current flowing from the drain node to the source node through the first switch circuit and the second switch circuit. In the power circuit, a first interconnection and a second interconnection of the interconnections are inductively coupled to balance the current flowing through the first switch circuit and the second switch circuit.

Abstract: Aspects of the disclosure provide a circuit for driving a power switch. The circuit includes a first circuit configured to provide a charging current to charge a control terminal of the power switch, a second circuit configured to provide a discharging current to discharge the control terminal of the power switch, and a control circuit configured to provide control signals to the first circuit and the second circuit to activate/deactivate the first circuit and the second circuit. At least one of the charging current and the discharging current ramps from a first level to a second level at a rate.

Abstract: Aspects of the disclosure provide a power circuit that includes a first switch circuit in parallel with a second switch circuit. The first switch circuit and the second switch circuit are coupled to a first driving node, a second driving node, a source node and a drain node via interconnections. The power circuit receives a control signal between the first driving node and the second driving node to control a current flowing from the drain node to the source node through the first switch circuit and the second switch circuit. In the power circuit, a first interconnection and a second interconnection of the interconnections are inductively coupled to balance the current flowing through the first switch circuit and the second switch circuit.

Abstract: Aspects of the disclosure provide a power device that includes an upper power module and a lower power module. The upper power module and the lower power module are coupled in series between two supply voltages, and are respectively controlled by a first control signal and a second control signal. Interconnections of the power device are inductively coupled to prevent reliability issues, such as crosstalk, self turn on, self sustained oscillation, and the like.

Abstract: The present invention generally provides methods and apparatus for monitoring performance of an injection valve. In one embodiment, a control signal relates to an actuator movement is monitored and correlated to performance of the injection valve.

Abstract: A method and apparatus for providing a precursor to a process chamber is described. The apparatus comprises an ampoule capable of receiving either a liquid precursor source material or a solid precursor source material. The ampoule is capable of delivering either a liquid precursor material to a vaporizer coupled to the process chamber, or a vaporized or gaseous precursor material to the process chamber. The ampoule also includes a continuous level sensor to accurately monitor the level of precursor source material within the ampoule.

Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Abstract: The present invention generally provides methods and apparatus for monitoring performance of an injection valve. In one embodiment, a control signal relates to an actuator movement is monitored and correlated to performance of the injection valve.