Abstract: A semiconductor package may include a package structure on a redistribution structure. The redistribution structure may include a wiring structure and an insulating structure covering the wiring structure. The package structure may include a semiconductor chip connected to the wiring structure. The insulating structure of the redistribution structure may include a plurality of first insulating layers and a second insulating layer between the plurality of first insulating layers. The plurality of first insulating layers may include at least one of a first conductive line pattern and a first conductive via pattern. The second insulating layer may include a second conductive line pattern overlapping the first conductive line pattern in a vertical direction.

Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.