Patents by Inventor Khaldoun Alzien

Khaldoun Alzien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8812169
    Abstract: In one embodiment, a printed circuit board assembly comprises a printed circuit board including a processor, a heat sink mountable to the printed circuit board proximate the processor, and a memory module comprising logic instructions which, when executed by the processor, configure the processor to initiate a processor load routine, collect temperature gradient data during the processor load routine, and verify operation of the heat sink using the temperature gradient data.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Phillip A. Leech, Khaldoun Alzien, William R. Jacobs
  • Patent number: 7647516
    Abstract: In a method for managing power consumption among compute nodes having respective power components, an increase in the power utilization of a first compute node of the compute nodes may be detected. In response to a detected increase, a sum of the power consumption levels of the compute nodes and the requested increase in power utilization of the first compute node is compared with an allowable power budget for a compute node pool. In addition, the power state of the first compute node power component is varied in response to the comparison.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: January 12, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Phillip Leech, Charles Shaver
  • Patent number: 7581125
    Abstract: A power management agent for managing power among electronic systems includes a module for predicting a future power consumption level of the electronic systems, a module for determining a power budget threshold for the electronic systems, and a module for determining whether a predicted future power consumption level will exceed the power budget threshold. The power management agent also includes a module for selecting one or more of the electronic systems to throttle in response to a determination that the predicted future power consumption level will exceed the power budget threshold and a module for selecting a throttle level to be applied to the selected one or more of the electronic systems to substantially prevent the future power consumption level from exceeding the power budget threshold.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 25, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Thomas Flynn, Phillip Leech, Charles Shaver
  • Patent number: 7529949
    Abstract: A system for managing heterogeneous supply of power includes a plurality of heterogeneous power supplies having a primary power supply and a secondary power supply. The primary power supply has a first power rating and the secondary power supply has a second power rating, where the first power rating differs from the second power rating. In addition, power is supplied to the electronic system through at least one of the primary power supply and the secondary power supply.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: May 5, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Phil Leech
  • Publication number: 20080184044
    Abstract: Embodiments include methods, apparatus, and systems for managing power consumption in a computer system. One embodiment includes a method that queries a blade for its power requirements when the blade is inserted into a blade computer enclosure. The method then determines, by the blade computer enclosure, whether the power requirements of the blade are within a power budget of the blade computer enclosure.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Phillip A. Leech, Khaldoun Alzien
  • Patent number: 7349828
    Abstract: In a method for estimating a condition of an electronic device, a model correlating at least one utilization metric of a component of the electronic device and the condition of the component to be estimated is formulated. In addition, the at least one utilization metric of the component is detected and the condition of the component and the electronic device are estimated based upon the formulated model with the detected at least one utilization metric as an input to the formulated model.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: March 25, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Phillip Leech
  • Patent number: 7336485
    Abstract: In one embodiment, a printed circuit board assembly comprises a heat sink having an electrically conductive mounting support and a printed circuit board including detection circuitry to detect an electrical connection between the electrically conductive mounting support and an electrically conductive receiver on the printed circuit board.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: February 26, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Phillip A. Leech, Kenneth B. Frame, Khaldoun Alzien
  • Publication number: 20070097620
    Abstract: In one embodiment, a printed circuit board assembly comprises a printed circuit board including a processor, a heat sink mountable to the printed circuit board proximate the processor, and a memory module comprising logic instructions which, when executed by the processor, configure the processor to initiate a processor load routine, collect temperature gradient data during the processor load routine, and verify operation of the heat sink using the temperature gradient data.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Phillip Leech, Khaldoun Alzien, William Jacobs
  • Publication number: 20070097622
    Abstract: In one embodiment, a printed circuit board assembly comprises a heat sink having an electrically conductive mounting support and a printed circuit board including detection circuitry to detect an electrical connection between the electrically conductive mounting support and an electrically conductive receiver on the printed circuit board.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Phillip Leech, Kenneth Frame, Khaldoun Alzien
  • Publication number: 20070067657
    Abstract: In a method for managing power consumption among compute nodes having respective power components, an increase in the power utilization of a first compute node of the compute nodes may be detected. In response to a detected increase, a sum of the power consumption levels of the compute nodes and the requested increase in power utilization of the first compute node is compared with an allowable power budget for a compute node pool. In addition, the power state of the first compute node power component is varied in response to the comparison.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Phillip Leech, Charles Shaver
  • Publication number: 20070067656
    Abstract: A power management agent for managing power among electronic systems includes a module for predicting a future power consumption level of the electronic systems, a module for determining a power budget threshold for the electronic systems, and a module for determining whether a predicted future power consumption level will exceed the power budget threshold. The power management agent also includes a module for selecting one or more of the electronic systems to throttle in response to a determination that the predicted future power consumption level will exceed the power budget threshold and a module for selecting a throttle level to be applied to the selected one or more of the electronic systems to substantially prevent the future power consumption level from exceeding the power budget threshold.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Inventors: Parthasarathy Ranganathan, Khaldoun Alzien, Thomas Flynn, Phillip Leech, Charles Shaver
  • Publication number: 20050213294
    Abstract: A plurality of interchangeable access panels each adapted to be removably attached to a partially-assembled chassis to occupy at least a portion of a vacant region of an exterior wall. Also, each access panel comprises a configuration of at least one aperture each constructed and arranged to provide operational access to components housed in the chassis.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 29, 2005
    Inventors: Jeff Lambert, Pete Austin, Michael Durham, Juan Perez, Khaldoun Alzien
  • Patent number: 6321307
    Abstract: A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a cycle to memory is initiated on the PCI or AGP bus by a peripheral device, a snoop control circuit of the bus bridge arbitrates for the processor bus to initiate a snoop cycle which corresponds to the line being accessed by the peripheral device. In addition to performing a snoop for the current line being accessed, the snoop control circuit further advantageously runs a speculative snoop cycle for the next sequential line. By performing a speculative snoop cycle on the CPU bus to the next line address, latencies associated with subsequent accesses to memory by the peripheral device may be reduced if the device performs a subsequent sequential access. Furthermore, since the bus bridge performs multiple snoop cycles per arbitration cycle (e.g.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: November 20, 2001
    Assignee: Compaq Computer Corporation
    Inventors: David J. Maguire, Khaldoun Alzien
  • Patent number: 6279087
    Abstract: A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: August 21, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Maria L. Melo, Khaldoun Alzien, Robert C. Elliott, David J. Maguire
  • Patent number: 6241400
    Abstract: A computer having a bus interface unit coupled between a CPU bus and a PCI bus and/or a bus interface unit coupled between a PCI bus and memory and or I/O space. The clocking to the configuration space of the bus interface unit can be inhibited to conserve power in two ways. The first approach relies on an input/output address space containing a configuration address register. An enable bit or flag within the configuration address register can be set to allow a determination of the various PCI devices and to configure those devices linked to the PCI bus. Subsequent to computer boot up or initialization, the enable bit can be disabled to disallow further accesses to the configuration address space of the PCI device or PCI compliant bus interface unit. Disabling the enable bit further inhibits or disconnects a clocking signal from sequential logic within the configuration address space to minimize power consumption of the north bridge during its normal operation.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 5, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Maria L. Melo, Khaldoun Alzien
  • Patent number: 6199131
    Abstract: A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: March 6, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Maria L. Melo, Khaldoun Alzien, Todd J. DeSchepper
  • Patent number: 5987555
    Abstract: A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 16, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Khaldoun Alzien, Maria L. Melo, Todd J. DeSchepper
  • Patent number: 5918026
    Abstract: A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater echoes transactions in either an upstream or downstream direction, and does not need any additional address decode logic. The buses are coupled to an arbiter so that only one bus master has control of the bus. During a burst operation, the PCI repeater causes the arbiter to cease providing grant signals to prospective bus grantees. The signal is removed only after the transaction has completed on both sides of the PCI repeater to ensure that the PCI repeater is ready for a next transaction.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: June 29, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Maria L. Melo, Khaldoun Alzien
  • Patent number: 5838932
    Abstract: A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater is operable to echo transactions in either an upstream or downstream direction. During configuration, the PCI repeater snoops configuration cycles on the primary bus to build an address map of devices on the primary bus. The PCI repeater then uses the address map as a lookup table as a positive determination of whether to forward a transaction upstream.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: November 17, 1998
    Assignee: Compaq Computer Corporation
    Inventor: Khaldoun Alzien
  • Patent number: 5802324
    Abstract: A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: September 1, 1998
    Assignee: Compaq Computer Corporation
    Inventors: Russell J. Wunderlich, Khaldoun Alzien