Abstract: A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made.

Abstract: A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output.

Abstract: An integrated circuit having a plurality of input/output modules, each of which has input/output modules including an input module section having an input node connected to a unique input/output pin on the integrated circuit and an output node communicating with a unique first internal node in the integrated circuit, and an output module section having an input node communicating with a unique second internal node in the integrated circuit and an output node communicating with the unique input/output pin. Each input/output module is programmable by a user such that its function may be defined as an input module, an output module, or a bi-directional module. The integrated circuit further has two states, a first unprogrammed state where none of the functions of the input/output modules have been defined, and a second, programmed state in which the functions of the input/output modules have been defined by either enabling or disabling the output section of the input/output module.

Abstract: In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.

Abstract: In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related t

Abstract: Apparatus for terminating unused input lines in a user-programmable interconnect architecture to one of a first voltage potential and a second voltage potential comprises at least one first tie-off conductor divided into at least two first segments and insulated from and intersecting the input lines, and at least one second tie-off conductor divided into at least two second segments and insulated from and intersecting the input lines. A plurality of first termination transistors each have their drains connected to a voltage rail for the first voltage potential and their sources connected to a different one of the first segments. A plurality of second termination transistors each have their sources connected to a voltage rail for the first voltage potential and their drains connected to a different one of the second segments. A termination transistor gate line is connected to the gates of each of the first and second termination transistors.

Abstract: A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output.

Abstract: Apparatus for testing for defects in the form of ohmic leakage in an antifuse element disposed between first and second conductors in an integrated circuit prior to formation of electronic circuits by a user, includes circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path to the first conductor during a first time period. Circuitry, responsive to signals provided to the integrated circuit from an external source, is provided to temporarily connect together a second group of the conductors to form a circuit path to the second conductor during the first time period. Circuitry is provided to place an electrical charge onto the first conductor during a second time period within the first time period such that a selected dynamic first voltage potential is placed on the first conductor.

Abstract: Apparatus for performing high voltage testing of high-voltage transistors in the programming paths of a user-configurable integrated circuit including a plurality of conductors which may be connected to one another and to functional circuit blocks by programming user-programmable antifuse elements connected thereto to form electronic circuits, prior to formation of the electronic circuits by a user, including circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path, the circuit path including the source and drain of at least one of the high-voltage transistors during a selected time period; circuitry for driving the circuit path and the gate of the at least one high-voltage transistor to a first voltage potential during the selected time period; circuitry for driving the bulk semiconductor region in the integrated circuit containing the source and drain of the at least one high-voltag

Abstract: A method to minimize disturbance of an already programmed antifuse while programming other antifuses in a circuit includes the steps of determining a preferred order in which to program the antifuses and programming them in the preferred order. High initial programming and soak currents are selected such that the disturb current is small with respect thereto. The magnitude of the disturb current is increased to a value that maintains the antifuse resistance or improves it rather than adversely affect it. Where a circuit node containing a first already programmed antifuse is positioned such that parasitic capacitances may discharge through that antifuse during the programming of a second antifuse, the magnitude of the charge stored at parasitic capacitances associated with the programming path is reduced by reducing the programming voltage when this programming situation is detected.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.

Abstract: A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

Abstract: In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related t

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conductive to custom circuit design.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segements connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conducive to custom circuit design.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.