Abstract: A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.

Abstract: The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.

Abstract: The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.

Abstract: The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.

Abstract: The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.

Abstract: A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.