Patents by Inventor Khalid EzzEldin Ismail
Khalid EzzEldin Ismail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7906413Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.Type: GrantFiled: April 28, 2006Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
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Patent number: 7083998Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.Type: GrantFiled: July 1, 2004Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
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Patent number: 7084431Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1?yGey, within a relaxed Si1?xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.Type: GrantFiled: April 26, 2004Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
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Patent number: 7067855Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 ? from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET'S, and HBT's.Type: GrantFiled: December 12, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
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Patent number: 6870232Abstract: A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned.Type: GrantFiled: April 17, 2000Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Jack Oon Chu, Khalid EzzEldin Ismail, Stephen Anthony Rishton, Katherine Lynn Saenger
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Patent number: 6858502Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.Type: GrantFiled: November 20, 2001Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
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Publication number: 20040227154Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1-yGey, within a relaxed Si1-xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.Type: ApplicationFiled: April 26, 2004Publication date: November 18, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
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Publication number: 20040185640Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET'S, and HBT's.Type: ApplicationFiled: December 12, 2003Publication date: September 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
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Patent number: 6784466Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.Type: GrantFiled: April 11, 2002Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
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Patent number: 6723621Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.Type: GrantFiled: June 30, 1997Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
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Publication number: 20020171077Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an nor p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.Type: ApplicationFiled: April 11, 2002Publication date: November 21, 2002Inventors: Jack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
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Publication number: 20020125475Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.Type: ApplicationFiled: November 20, 2001Publication date: September 12, 2002Inventors: Jack Oon Chu, Richard Hammond, Khalid Ezzeldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
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Patent number: 6425951Abstract: An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400° C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.Type: GrantFiled: August 6, 1999Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail
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Patent number: 6350993Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.Type: GrantFiled: March 12, 1999Date of Patent: February 26, 2002Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
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Patent number: 6251751Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.Type: GrantFiled: April 13, 1999Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail, Kim Yang Lee, John Albrecht Ott
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Patent number: 6096590Abstract: A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned. The invention overcomes the problem of self-aligned high resistance source/drain contacts and a high resistance gate electrode for submicron FET devices which increase as devices are scaled to smaller dimensions.Type: GrantFiled: June 30, 1998Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Jack Oon Chu, Khalid EzzEldin Ismail, Stephen Anthony Rishton, Katherine Lynn Saenger
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Patent number: 6059895Abstract: An SOI substrate and method for forming is described incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si and/or S.sub.i O.sub.2 over the strained layers, bonding a second substrate having an insulating layer on its upper surface to the top surface above the strained layers, and removing the first substrate. The invention overcomes the problem of forming strained Si and SiGe layers on insulating substrates.Type: GrantFiled: May 13, 1999Date of Patent: May 9, 2000Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid EzzEldin Ismail
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Patent number: 6013134Abstract: An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400.degree. C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.Type: GrantFiled: February 18, 1998Date of Patent: January 11, 2000Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail
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Patent number: 5963817Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.Type: GrantFiled: October 16, 1997Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Khalid Ezzeldin Ismail, Kim Yang Lee, John Albrecht Ott
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Patent number: 5955759Abstract: A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.Type: GrantFiled: December 11, 1997Date of Patent: September 21, 1999Assignee: International Business Machines CorporationInventors: Khalid EzzEldin Ismail, Stephen Anthony Rishton, Katherine Lynn Saenger