Patents by Inventor Khalid M. Sirajuddin

Khalid M. Sirajuddin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9023227
    Abstract: Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jivko Dinev, Saravjeet Singh, Khalid M. Sirajuddin, Tong Liu, Puneet Bajaj, Rohit Mishra, Sonal A. Srivastava, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20130288474
    Abstract: Methods for fabricating dual damascene interconnect structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include etching a via into a substrate through a first photoresist layer; patterning a second photoresist layer atop the substrate to define a trench pattern, wherein the via is aligned within the trench pattern, and wherein a portion of undeveloped photoresist remains in the via after patterning; and etching the trench into the substrate to form a dual damascene pattern in the substrate.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: ROHIT MISHRA, JAYAGATAN R. VIJAYEN, KHALID M. SIRAJUDDIN, BRAD EATON, MADHAVA RAO YALAMANCHILI
  • Publication number: 20130005152
    Abstract: Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).
    Type: Application
    Filed: May 25, 2012
    Publication date: January 3, 2013
    Applicant: Applied Materials, Inc.
    Inventors: JIVKO DINEV, Saravjeet Singh, Khalid M. Sirajuddin, Tong Liu, Puneet Bajaj, Rohit Mishra, Sonal A. Srivastava, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 8158522
    Abstract: Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: April 17, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Khalid M. Sirajuddin, Digvijay Raorane, Jon C. Farr, Sharma V. Pamarthy
  • Publication number: 20110217832
    Abstract: Methods of filling deep trenches in substrates are described. A method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process.
    Type: Application
    Filed: September 10, 2010
    Publication date: September 8, 2011
    Inventors: Digvijay Raorane, Khalid M. Sirajuddin, Jon C. Farr, Sharma V. Pamarthy
  • Publication number: 20110201205
    Abstract: Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.
    Type: Application
    Filed: September 10, 2010
    Publication date: August 18, 2011
    Inventors: Khalid M. Sirajuddin, Digvijay Raorane, Jon C. Farr, Sharma V. Pamarthy